Datasheet
1
2
3
4
DAC128S085
V
OUTA
V
OUTB
V
OUTC
V
OUTD
GND
V
A
V
REF2
V
REF1
8
7
6
5
13
14
15
DIN
SCLK
SYNC
16
D
OUT
9
10
11
V
OUTG
12
V
OUTF
V
OUTH
V
OUTE
1
2
3
4
13
14
15
SCLK
DAC128S085
SYNC
V
OUTA
16
5
6
7
8
V
A
9
10
11
V
OUTG
12
V
OUTB
V
OUTC
V
OUTD
V
REF1
V
OUTF
V
OUTH
V
OUTE
GND
V
REF2
D
IN
D
OUT
DAC128S085
www.ti.com
SNAS407F –AUGUST 2007–REVISED MARCH 2013
PIN CONFIGURATION
Pin Descriptions
WQFN TSSOP
Symbol Type Description
Pin No. Pin No.
1 3 V
OUTA
Analog Output Channel A Analog Output Voltage.
2 4 V
OUTB
Analog Output Channel B Analog Output Voltage.
3 5 V
OUTC
Analog Output Channel C Analog Output Voltage.
4 6 V
OUTD
Analog Output Channel D Analog Output Voltage.
5 7 V
A
Supply Power supply input. Must be decoupled to GND.
Unbuffered reference voltage shared by Channels A, B, C, and D.
6 8 V
REF1
Analog Input
Must be decoupled to GND.
Unbuffered reference voltage shared by Channels E, F, G, and H.
7 9 V
REF2
Analog Input
Must be decoupled to GND.
8 10 GND Ground Ground reference for all on-chip circuitry.
9 11 V
OUTH
Analog Output Channel H Analog Output Voltage.
10 12 V
OUTG
Analog Output Channel G Analog Output Voltage.
11 13 V
OUTF
Analog Output Channel F Analog Output Voltage.
12 14 V
OUTE
Analog Output Channel E Analog Output Voltage.
Frame Synchronization Input. When this pin goes low, data is written
into the DAC's input shift register on the falling edges of SCLK. After
the 16th falling edge of SCLK, a rising edge of SYNC causes the
13 15 SYNC Digital Input
DAC to be updated. If SYNC is brought high before the 15th falling
edge of SCLK, the rising edge of SYNC acts as an interrupt and the
write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the
14 16 SCLK Digital Input
falling edges of this pin.
Serial Data Input. Data is clocked into the 16-bit shift register on the
15 1 D
IN
Digital Input
falling edges of SCLK after the fall of SYNC.
Serial Data Output. D
OUT
is utilized in daisy chain operation and is
connected directly to a D
IN
pin on another DAC128S085. Data is not
16 2 D
OUT
Digital Output
available at D
OUT
unless SYNC remains low for more than 16 SCLK
cycles.
Exposed die attach pad can be connected to ground or left floating.
PAD
17 Ground Soldering the pad to the PCB offers optimal thermal performance
(WQFN only)
and enhances package self-alignment during reflow.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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