Datasheet

DAC128S085

www.ti.com

SNAS407F –AUGUST 2007–REVISED MARCH 2013

POWER-ON RESET

The power-on reset circuit controls the output voltages of the eight DACs during power-up. Upon application of

power, the DAC registers are filled with zeros and the output voltages are set to 0V. The outputs remain at 0V

until a valid write sequence is made.

POWER-DOWN MODES

The DAC128S085 has three power-down modes where different output terminations can be selected (see

Table 4). With all channels powered down, the supply current drops to 0.1 µA at 3V and 0.2 µA at 5V. By

selecting the channels to be powered down in DB[7:0] with a "1", individual channels can be powered down

separately or multiple channels can be powered down simultaneously. The three different output terminations

include high output impedance, 100k ohm to ground, and 2.5k ohm to ground.

The output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the power-down

modes. The bias generator, however, is only shut down if all the channels are placed in power-down mode. The

contents of the DAC registers are unaffected when in power-down. Therefore, each DAC register maintains its

value prior to the DAC128S085 being powered down unless it is changed during the write sequence which

instructed it to recover from power down. Minimum power consumption is achieved in the power-down mode with

SYNC idled high, D

idled low, and SCLK disabled. The time to exit power-down (Wake-Up Time) is typically 3

µsec at 3V and 20 µsec at 5V.

Table 4. Power-Down Modes

DB[15:12] DB[11:8] 7 6 5 4 3 2 1 0 Output Impedance

1 1 0 1 X X X X H G F E D C B A High-Z outputs

1 1 1 0 X X X X H G F E D C B A 100 kΩ outputs

1 1 1 1 X X X X H G F E D C B A 2.5 kΩ outputs

Product Folder Links: DAC128S085