Datasheet

DAC 3
D
IN1
SYNC
DAC 2 DAC 1
DAC 3 DAC 2
DAC 3
D
IN2
/D
OUT1
D
IN3
/D
OUT2
Data Loaded into the DACs
48 SCLK Cycles (16 X 3)
15
th
SCLK Cycle 31
st
SCLK Cycle
DAC 1
SCLK
D
IN
SYNC
D
OUT
DAC 2
SCLK
D
IN
SYNC
D
OUT
DAC 3
SCLK
D
IN
SYNC
D
OUT
SCLK
D
IN
SYNC
DAC128S085
SNAS407F –AUGUST 2007–REVISED MARCH 2013 www.ti.com
Figure 30. Daisy Chain Configuration
The serial data output pin, D
OUT
, is available on the DAC128S085 to allow daisy-chaining of multiple
DAC128S085 devices in a system. In a write sequence, D
OUT
remains low for the first fourteen falling edges of
SCLK before going high on the fifteenth falling edge. Subsequently, the next sixteen falling edges of SCLK will
output the first sixteen data bits entered into D
IN
. Figure 31 shows the timing of three DAC128S085s in
Figure 30. In this instance, It takes forty-eight falling edges of SCLK followed by a rising edge of SYNC to load all
three DAC128S085s with the appropriate register data. On the rising edge of SYNC, the programmed function is
executed in each DAC128S085 simultaneously.
When connecting multiple devices in a daisy chain configuration it is important to note that the DAC128S085 will
update the D
OUT
signal on the falling edge of SCLK, and this will be sampled by the next DAC in the daisy chain
on the next falling edge of the clock. Ensure that the timing requirements are met for proper operation.
Specifically pay attention to the data hold time after SCLK falling (t
DH
) requirement. There is a risk due to
improper layout or loading that the clock signal can be delayed between devices. If delayed to the point that data
changes prior to meeting the hold time requirement this will cause incorrect data to be sampled. If the clock delay
can’t be resolved an alternative solution could be to add a delay between the D
OUT
of one device and D
IN
of the
following device in the daisy chain. This will increase the hold time margin and allow for correct sampling. Be
aware though, that the tradeoff with this fix is that too much delay will eventually impact the set up time.
Figure 31. Daisy Chain Timing Diagram
SERIAL INPUT REGISTER
The DAC128S085 has two modes of operation plus a few special command operations. The two modes of
operation are Write Register Mode (WRM) and Write Through Mode (WTM). For the rest of this document, these
modes will be referred to as WRM and WTM. The special command operations are separate from WRM and
WTM because they can be called upon regardless of the current mode of operation. The mode of operation is
controlled by the first four bits of the control register, DB15 through DB12. See Table 1 for a detailed summary.
Table 1. Write Register and Write Through Modes
DB[15:12] DB[11:0] Description of Mode
1 0 0 0 X X X X X X X X X X X X WRM: The registers of each DAC Channel can be written to without causing
their outputs to change.
1 0 0 1 X X X X X X X X X X X X WTM: Writing data to a channel's register causes the DAC output to change.
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