Datasheet

1 2
3 4
5
6
7 8
CLK
TDATA
t
CTHD
t
TSOP
t
TCSU
t
SCSU
t
CPW
t
CPW
t
CLK
DAC OUTPUT
21
TDATA
Sample
9
Next TDATA
Sample
t
SYLW
t
STDAT
t
TDATA
SYNC
Output
Hold
Output
Update
DAC1280
www.ti.com SBAS432A –APRIL 2010–REVISED SEPTEMBER 2010
TIMING CHARACTERISTICS
space
Figure 1.
TIMING REQUIREMENTS
At T
A
= –40°C to +85°C and DVDD = 1.65V to 3.6V.
PARAMETER MIN TYP MAX UNIT
t
CLK
CLK period (1/f
CLK
) 240 1000 ns
t
CPW
CLK high or low pulse width 100 ns
t
SCSU
SYNC rising edge to CLK rising edge setup time 30 ns
t
TCSU
TDATA to CLK rising edge setup time 30 ns
t
CTHD
CLK rising edge to TDATA hold time 10 ns
t
SYLW
SYNC low pulse width 2 t
CLK
t
STDAT
Rising CLK after SYNC high to TDATA sample time 5 t
CLK
t
TSOP
TDATA sample to output update 4 t
CLK
t
TDATA
TDATA period 16 t
CLK
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