Datasheet

DAC1280
SBAS432A –APRIL 2010–REVISED SEPTEMBER 2010 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information see the Package Option Addendum at the end of this
document, or see the device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range, unless otherwise noted.
DAC1280
MIN MAX UNIT
AVDD to AVSS –0.3 +5.5 V
AVSS to DGND –2.8 +0.3 V
DVDD to DGND –0.3 +3.6 V
Input current, momentary –100 +100 mA
Input current, continuous –10 +10 mA
Analog input or output voltage to DGND AVSS – 0.3 AVDD + 0.3 V
Digital input voltage to DGND –0.3 DVDD + 0.3 V
Maximum junction temperature +150 °C
Operating temperature range –40 +125 °C
Storage temperature range –60 +150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
THERMAL INFORMATION
DAC1280
THERMAL METRIC
(1)
TSSOP UNITS
16 PINS
q
JA
Junction-to-ambient thermal resistance
(2)
111.9
q
JCtop
Junction-to-case (top) thermal resistance
(3)
33.3
q
JB
Junction-to-board thermal resistance
(4)
52.4
°C/W
y
JT
Junction-to-top characterization parameter
(5)
2.0
y
JB
Junction-to-board characterization parameter
(6)
51.2
q
JCbot
Junction-to-case (bottom) thermal resistance
(7)
—
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, y
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, y
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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