Datasheet

DAC1280
SBAS432A –APRIL 2010–REVISED SEPTEMBER 2010 www.ti.com
Pin Descriptions TDATA bits are '1'), the differential output current is at
a positive maximum value; when the 1s density input
GAIN[2:0] Pins is at 25% (on average, three out of four TDATA bits
are '0'), the differential output current is at a negative
The DAC1280 output range can be set in 6dB steps,
maximum value. When the 1s density is 50% (on
controlled by three digital inputs. The ranges match
average, an equal number of '1's and '0's), the
the gains of the ADS1282 for testing at all gains.
differential output current is 0. See Table 1.
Table 2 shows the output range versus gain settings
for the DAC1280. TDATA is sampled by the DAC1280 at CLK/16 rate
(nominally 256kHz with 4.096MHz master clock), and
NOTE: It is recommended that the DAC and ADC
therefore, the sampling of TDATA can have 16 CLK
use complementary gains when testing. ADC
cycles of uncertainty. SYNC can be used to eliminate
instability may result because of the combination of
the uncertainty by synchronizing TDATA sampling.
the noise-shaped DAC input and if the ratio of
Synchronizing TDATA sampling yields a consistent
ADC/DAC gain is greater than 2.
test signal phase response.
IOUTP, IOUTN
SYNC
IOUTP and IOUTN are the differential current
SYNC is an input used to synchronize the CLK cycle
outputs. The outputs are intended to be used in
at which the DAC1280 samples TDATA. When SYNC
conjunction with an external current-to-voltage
is low, the internal CLK is disabled (ignoring TDATA
converter, as shown in the circuit of Figure 35. Note
input), and the DAC output is held constant. When
that the current-to-voltage converter also sets the
SYNC is taken high, the DAC resumes sampling
DAC1280 DAC output common-mode voltage. See
TDATA on the sixth rising CLK edge after SYNC is
specifications for the allowable common-mode output
high. TDATA is then sampled on periodic 16 CLK
voltage.
intervals. Four CLK cycles propagate from the
TDATA sample to the physical update of the DAC
CLK
output. If SYNC is not used, tie SYNC high. Refer to
Figure 1 for an illustration of the SYNC timing
CLK is the master clock input to the DAC1280
sequence.
(nominally 4.096MHz). As with any high-performance
ADC or DAC, a high-quality, low-jitter clock source is
PWDN
essential. A crystal oscillator clock source is
recommended. Make sure to avoid excess ringing on
PWDN is an input used to power down the DAC1280.
the clock input: keeping the printed circuit board
To power down the device, take the PWDN pin low.
(PCB) trace short, and using source termination
In power-down mode, the device bias is disabled and
resistors (20Ω to 50Ω) placed close to the source
the outputs are Hi-Z. Note that the digital inputs must
end, often helps.
remain defined in power-down mode either as logic
low or logic high; do not float the inputs. Disable the
TDATA
CLK and TDATA inputs to minimize power-supply
leakage. To exit power-down mode, take PWDN high.
TDATA is the digital signal input and determines the
The DAC1280 output is reset to zero when the
output frequency and amplitude. TDATA is encoded
PWDN pin goes high.
as a 1s density bitstream where the DAC1280 output
is proportional to the 1s density. When the 1s density
input is 75% (that is, on average, three out of four
Table 2. Differential Current Output vs Gain Setting
(1)
GAIN[2:0] PINS GAIN GAIN (dB) IOUTP – IOUTN (mA) V
P
– V
N
(V)
000 1/1 0 ±1250 ±2.5
001 1/2 –6 ±625 ±1.25
010 1/4 –12 ±312 ±0.625
011 1/8 –18 ±156 ±0.312
100 1/16 –24 ±78.1 ±0.156
101 1/32 –30 ±39.1 ±0.0781
110 1/64 –36 ±19.5 ±0.0391
(1) TDATA 1s density 25%/75%, V
REF
= 5V, R
REF
= 30kΩ, external current-to-voltage converter resistors = 2kΩ. Output current and voltage
are differential. Excludes the effects of DAC1280 offset, gain and linearity errors, errors in reference voltage, errors caused by external
resistors, and errors as a result of external current-to-voltage conversion. See Figure 27.
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