Datasheet

t
XIN
t
1
X
IN
t
2
t
3
t
4
t
5
t
7
t
6
t
8
SCLK
SDIO
DAC1220
www.ti.com ...................................................................................................................................... SBAS082G –FEBRUARY 1998–REVISED SEPTEMBER 2009
DIGITAL INTERFACE
Timing
The serial interface is synchronous and controlled by the SCLK input. The DAC1220 latches incoming bits on the
falling edge of SCLK, and shifts outgoing bits on the rising edge of SCLK. An external interface should shift
outgoing bits on the rising edge of SCLK, and latch incoming bits on the falling edge of SCLK. The relevant
waveforms are illustrated in the timing diagrams (see Figure 7 to Figure 11). Timing numbers are given in
Table 2 through Table 4.
Figure 7. X
IN
Clock Timing
Table 2. X
IN
Timing Characteristics
SYMBOL DESCRIPTION MIN NOM MAX UNITS
f
XIN
X
IN
clock frequency 1 2.5 MHz
t
XIN
X
IN
clock period 400 1000 ns
t
1
X
IN
clock high 0.4 × t
XIN
ns
t
2
X
IN
clock low 0.4 × t
XIN
ns
Figure 8. Serial Input/Output Timing
Table 3. Serial I/O Timing Characteristics
SYMBOL DESCRIPTION MIN NOM MAX UNITS
t
3
SCLK high 5 × t
XIN
ns
t
4
SCLK low 5 × t
XIN
ns
t
5
Data in valid to SCLK falling edge (setup) 40 ns
t
6
SCLK falling edge to data in not valid (hold) 20 ns
t
7
Data out valid to rising edge of SCLK (hold) 0 ns
t
8
SCLK rising edge to new data out valid (delay) 50 ns
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