Datasheet

5V
Analog
Supply
5V
Digital
Supply
DV
DD
AV
DD
DAC1220
SBAS082G –FEBRUARY 1998–REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
Serial Interface Most designs will use a single power supply for AV
DD
and DV
DD
. In these designs, the supplies ramp
The DAC1220 can be operated from most SPI
simultaneously, which is acceptable. In those designs
peripherals, or it can be bit-banged.
that use separate sources for AV
DD
and DV
DD
, the
two supplies must be sequenced properly. This is
Note that if SDIO is operated bidirectionally, it may be
easily done using a Schottky diode, as shown in
necessary to place a pullup resistor on the line, so
Figure 6. The diode ensures that DV
DD
will not
that the line will not be floating.
exceed AV
DD
by more than a Schottky diode drop.
The serial clock is limited to one-tenth of the master
clock frequency. For a 2.4576MHz master clock, the
Brownouts and Power-On Reset
serial clock may be no faster than 245.76kHz. The
designer should bear this in mind, as it may prevent The DAC1220 incorporates a power-on reset (POR)
the DAC1220 from being shared with other SPI circuit. The circuit will trigger as long as the power
devices or placed on an SPI bus, which may run supply ramps up at 50mV/ms or faster. If the power
much faster. supply ramps more slowly than this, the POR may not
trigger.
If the DAC1220 is placed on a shared SPI bus, the
chip-select line must be controlled; otherwise, it can The DAC1220 does not have a brownout detector.
be grounded. The POR circuit will not retrigger unless the supply
voltages have approached ground. Because of this, if
Although the SDIO line is bidirectional, it can be
the supply falls to a low voltage, it may corrupt the
operated as an input only, as long as no register
logic of the DAC1220, causing it to operate erratically
reads are performed. The DAC1220 can be operated
or to fail entirely. It may be necessary to forcibly
without register reads, although for situations
discharge the supply, since the DAC1220 may
requiring high reliability, this is not recommended,
occasionally fail to detect the SCLK reset pattern in
since the device registers and operation cannot be
this condition.
directly verified.
The SCLK reset pattern serves in place of a reset
pin. See the SCLK Reset Pattern section for
Power Supplies
information.
The DAC1220 has separate analog and digital power
supply connections. Both are intended to operate at
Supply Decoupling
+5V.
Both supply pins should be heavily decoupled at the
The digital supply must never exceed the analog
device for best performance. A 10μF multi-layer
supply by more than 300mV. If it does, the DAC1220
ceramic capacitor can be used for this, or a tantalum
may be permanently damaged. The analog supply
capacitor in parallel with a small (0.1μF) ceramic
may be greater than the digital supply without
capacitor can be used. Both capacitors, particularly
damage, however.
the ceramic capacitor, should be placed as close to
the pins as possible being decoupled.
Figure 6. Supply Sequence Protection
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