Datasheet
DV
DD
X
OUT
X
IN
DGND
AV
DD
DNC
DNC
DNC
SCLK
SDIO
CS
AGND
V
REF
V
OUT
C
2
C
1
12pF
(1)
12pF
(1)
4.7
µ
F
Ceramic
2.5MHz
+2.5V from
Voltage Reference
V
OUT
SPI CLOCK
SPI DATA
From Chip Select or Ground
+5V
C
2
(2)
C
1
(2)
4.7
µ
F
Ceramic
+5V
NOTES: (1) Depends on crystal and board layout. (2) See text for recommended values.
DAC1220
SBAS082G –FEBRUARY 1998–REVISED SEPTEMBER 2009......................................................................................................................................
www.ti.com
THEORY OF OPERATION
Self-Calibration System
The DAC1220 is a monolithic 20-bit delta-sigma (ΔΣ)
digital-to-analog converter (DAC) designed for The self-calibration system of the DAC1220
applications requiring extremely high precision. The measures the DAC output and calculates appropriate
delta-sigma topology used in the DAC1220 ensures gain and offset calibration constants. The output
20-bit monotonicity over the industrial temperature changes during calibration, but can optionally be
range. The DAC1220 can also be operated in 16-bit disconnected during the procedure.
mode, which gives a faster settling time at the
Offset calibration is performed by setting the DAC
expense of higher noise.
output voltage to mid-scale and repeatedly comparing
The core of the DAC1220 consists of an interpolation the DAC output to the V
REF
voltage using an
filter and a second-order delta-sigma modulator. The auto-zeroed comparator, which is re-zeroed after
output of the modulator is passed to a first-order every comparison. The comparator results are
switched-capacitor filter in series with a second-order recorded and averaged, two’s complement adjusted,
continuous-time filter, which generates the output and placed in the Offset Calibration Register.
voltage.
Gain calibration is performed in a similar way, except
To increase settling time, the DAC1220 can adjust its that the correction is done against an
filter cutoff frequency when it detects a voltage output internally-generated reference voltage, and the final
step of greater than approximately 40mV. This register value is calculated differently. The Full-Scale
behavior can be disabled. Calibration Register result represents the gain code
and is not two’s complement adjusted. Changing the
An onboard self-calibration facility compensates for
Gain Register value can change the range of
internal offset and gain errors. Calibration values may
voltages that are output for the same digital codes,
be stored and loaded externally if desired.
centered on V
REF
.
The DAC1220 can be put into a sleep mode, in which
power consumption is cut by about 1/6 to BASIC CONNECTIONS
approximately 0.45mW. In sleep mode, the output is
A schematic showing basic connections to the
disconnected.
DAC1220 is given in Figure 5.
The DAC1220 is controlled using a synchronous
serial interface, using either two or three wires. The
interface may be operated bidirectionally or
unidirectionally; readback is optional.
Figure 5. DAC1220 Schematic
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