Datasheet

DAC1220
SBAS082G –FEBRUARY 1998–REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
APPLICATION INFORMATION
Note that the delays are slightly different if chip-select
Layout Recommendations
(CS) is not being used.
The DAC1220 is a high-precision analog component
Timing delays from the beginning of an SPI byte
incorporating digital elements. Achieving good
transmission are a common problem in
precision is not difficult, but achieving excellent
microcontroller firmware that uses an SPI peripheral.
precision may require several attempts.
Be sure that any delay routine begins once a byte
has completed transmission, or add the byte
It is critical to supply a guard ring, or fill, around the
transmission time to the delay time.
C
1
and C
2
pins. The guard ring should be connected
to the voltage reference. These nodes are very
Some programmers may find that bit-banging, or
sensitive, and are good places for noise to couple
direct manipulation of microcontroller I/O pins, is the
through to the output. A ground fill on the opposite
easiest way to communicate with the DAC1220,
side of the board, or a ground plane, is also a good
because of the delays and direction changes
idea.
required.
The capacitors themselves should be placed as near
the pins as possible. In particular, the traces leading Write-Only Interfacing
from C
1
and C
2
should be kept very short. The traces
In some situations, such as isolated interfacing, it is
leading to V
OUT
and V
REF
can be longer.
inconvenient to use the DAC1220 bidirectionally,
It is also very important to route digital traces away since the SDIO pin changes direction for readback.
from analog traces, so that their associated return The DAC1220 can be used write-only. The following
currents will not couple into the analog side. considerations apply:
• When used write-only, it is not possible to verify
If a crystal is used, do not route the traces connecting
that the DAC1220 is operating using its serial
the crystal to the device through vias, if possible,
interface alone. The operation of the DAC is
because this will increase the trace inductance and
open-loop.
may affect startup and reliability. Keep the traces
• It may be helpful to wait at least 150ms-200ms
short, and place the crystal close to the device. Keep
after startup. This ensures that, in case the reset
in mind that extra ground planes and trace lengths
was a result of firmware problems and not
increase parasitic capacitance, and this should be
power-up, any previous communication with the
deducted from the load capacitor values.
DAC has been cancelled by the I/O recovery
timeout.
Software Considerations
• When applying the SCLK reset pattern, which can
A key to communicating successfully with the
be done in place of the above steps, allow time for
DAC1220 is observing the delays in the interface
the oscillator to start before applying the pattern.
timing diagrams. A violation of these delays, at best,
The pattern is detected based on oscillator cycles,
results in lack of correct output; at worse, violating the
so it will not be detected if the oscillator is not yet
delays can corrupt communications entirely.
running.
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