Datasheet
DAC1220
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...................................................................................................................................... SBAS082G –FEBRUARY 1998–REVISED SEPTEMBER 2009
Fast Settling Mode
To speed up settling, the DAC1220 can change the REGISTERS
cutoff frequency of its output filter. Raising the cutoff
The register map is shown in Table 11.
frequency causes the DAC1220 to settle faster, but at
the expense of higher noise. The adaptive filtering
Table 11. Register Memory Map
mode provides a good compromise by increasing the
ADDRESS CONTENT
filter frequency only while the DAC is changing its
output by more than approximately 40mV. When the
0 DIR byte 2 (MSB)
output has settled, the filter frequency is reduced
1 DIR byte 1
again.
2 DIR byte 0 (LSB)
Adaptive filtering is controlled by the ADPT and DISF
3 Reserved
bits in the Command Register. The action of these
4 CMR byte 1 (MSB)
bits together is described in Table 10.
5 CMR byte 0 (LSB)
6 Reserved
Table 10. Fast Settling Modes
7 Reserved
ADPT DISF
8 OCR byte 2 (MSB)
(CMR bit 15) (CMR bit 4) FAST SETTLING MODE
9 OCR byte 1
0 0 Fast settling only during > 40mV
step
10 OCR byte 0 (LSB)
0 1 Disabled
11 Reserved
1 0 Fast settling always on (filter cutoff
12 FCR byte 2 (MSB)
increased)
13 FCR byte 1
1 1 Disabled
14 FCR byte 0 (LSB)
space
15 Reserved
Command Register (CMR)
The command register contains the configuration bits of the DAC1220. It is shown in Table 12. The bits in the
command register are shown in Table 13.
Writes to the CMR take effect at the negative edge of SCLK during the last bit of the last byte of the write
command.
blank
Table 12. Command Register
15 14 13 12 11 10 9 8
ADPT CALPIN Reserved Reserved Reserved Reserved CRST Reserved
R/W-0 R/W-0 R-1
(1)
R-0 R-1 R-0 R/W-0 R-0
(1) In early versions of the DAC1220, this bit was rw-0. See the Calibration section for details.
7 6 5 4 3 2 1 0
RES CLR DF DISF BD MSB MD
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-10b
LEGEND: R = Read, W = Write
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