Datasheet

t
16
t
18
t
19
t
17
t
17
SCLK
Reset On
Falling Edge
DAC1220
www.ti.com ...................................................................................................................................... SBAS082G –FEBRUARY 1998–REVISED SEPTEMBER 2009
The chip-select pin CS is active low. When CS is SCLK Reset Pattern
high, activity on SCLK is ignored. There are certain
The DAC1220 does not have a dedicated reset pin.
timing limits and delays which apply to the
Instead, it contains a circuit which waits for a special
manipulation of CS, as shown in Figure 10. These
pattern to appear on SCLK, and triggers the internal
must be observed, or the DAC1220 may malfunction.
hardware reset line when it detects the special
If CS is not used, it should be tied low. When CS is pattern.
tied low, different timing limits and delays must be
This pattern, called the SCLK reset pattern, is shown
observed, as shown in Figure 9. If these are violated,
in Figure 12, with timing information given in Table 5.
the DAC1220 may malfunction.
The pattern is very different from the usual clocking
The serial interface is byte-oriented. All data is patterns which appear on SCLK, and is unlikely to be
transferred in groups of eight bits. detected by accident during normal operation.
The SCLK reset pattern can only be triggered when
I/O Recovery
CS is low. When CS is high, the SCLK line is ignored,
and the SCLK reset pattern is not detected.
The DAC1220 has a timeout on the serial interface. If
f
CLK
is 2.5MHz, the timeout is approximately 100ms.
At 2.5MHz, if a command is interrupted, and no
activity occurs on the SCLK or CS lines for 100ms,
the DAC1220 will cancel the command. If the
command was a write command, no registers are
affected.
The timeout period scales with the frequency of f
CLK
.
Figure 12. Resetting the DAC1220
Table 5. Reset Timing Characteristics
SYMBOL DESCRIPTION MIN NOM MAX UNITS
t
16
First high period 512 × t
XIN
800 × t
XIN
ns
t
17
Low period 10 × t
XIN
ns
t
18
Second high period 1024 × t
XIN
1800 × t
XIN
ns
t
19
Third high period 2048 × t
XIN
2400 × t
XIN
ns
Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): DAC1220