Datasheet

POWER-ON
RESET
DAC
REGISTER
INPUT
CONTROL
LOGIC
12-BIT DAC
12
12
POWER-DOWN
CONTROL
LOGIC
BUFFER
1k 100k
SCLK
D
IN
SYNC
REF(+) REF(-)
V
A
GND
DAC121S101
V
OUT
SOT
D
IN
SCLK
V
A
GND
V
OUT
1
2
3
6
5
4
SYNC
VSSOP
1
2
3
4
8
7
6
5
GND
D
IN
SCLK
V
A
NC
NC
V
OUT
SYNC
DAC121S101
SNAS265I –JUNE 2005–REVISED MARCH 2013 www.ti.com
Pin Configuration
Block Diagram
Pin Functions
Pin Descriptions
SOT
VSSOP
(SOT-23) Symbol Description
Pin No.
Pin No.
1 4 V
OUT
DAC Analog Output Voltage.
2 8 GND Ground reference for all on-chip circuitry.
3 1 V
A
Power supply and Reference input. Should be decoupled to GND.
Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after
4 7 D
IN
the fall of SYNC.
5 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin.
Frame synchronization input for the data input. When this pin goes low, it enables the input shift
register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th
6 5 SYNC
clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the DAC.
2, 3 NC No Connect. There is no internal connection to these pins.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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