Datasheet

V
A
R
R
R
R
To Output Amplifier
R
DAC121S101
www.ti.com SNAS265I –JUNE 2005–REVISED MARCH 2013
Figure 35. DAC Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0V to V
A
. All amplifiers, even
rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and V
A
, in this case). For
this reason, linearity is specified over less than the full output range of the DAC. The output capabilities of the
amplifier are described in the Electrical Characteristics.
SERIAL INTERFACE
The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs. See the Timing
Diagram for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the D
IN
line is clocked
into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is
clocked in and the programmed function (a change in the mode of operation and/or a change in the DAC register
contents) is executed. At this point the SYNC line may be kept low or brought high. In either case, it must be
brought high for the minimum specified time before the next write sequence as a falling edge of SYNC can
initiate the next write cycle.
Since the SYNC and D
IN
buffers draw more current when they are high, they should be idled low between write
sequences to minimize power consumption.
INPUT SHIFT REGISTER
The input shift register, Figure 36, has sixteen bits. The first two bits are "don't cares" and are followed by two
bits that determine the mode of operation (normal mode or one of three power-down modes). The contents of the
serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Timing
Diagram, Figure 2.
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