Datasheet
DAC121C081, DAC121C085
www.ti.com
SNAS395D –DECEMBER 2007–REVISED MARCH 2013
Electrical Characteristics (continued)
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for V
A
= +2.7V to +5.5V, V
REF
= V
A
, C
L
= 200 pF to GND, input code range 48 to 4047.
Boldface limits apply for T
MIN
≤ T
A
≤ T
MAX
and all other limits are at T
A
= 25°C, unless otherwise specified.
Units
Symbol Parameter Conditions Typical
(1)
Limits
(1)
(Limits)
Power Down -- 2-wire interface quiet (SCL = SDA = V
A
) after PD mode written to DAC register. (output unloaded)
V
A
= 2.7V to 3.6V 0.13 1.52 µA (max)
Supply Current
I
PD
All Power Down Modes
(V
A
& V
REF
for DAC121C085)
V
A
= 4.5V to 5.5V 0.15 3.25 µA (max)
V
A
= 3.0V 0.5 µW
Power Consumption
P
PD
All Power Down Modes
(V
A
& V
REF
for DAC121C085)
V
A
= 5.0V 0.9 µW
A.C. and Timing Characteristics
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for V
A
= +2.7V to +5.5V, V
REF
= V
A
, R
L
= Infinity, C
L
= 200 pF to GND. Boldface limits
apply for T
MIN
≤ T
A
≤ T
MAX
and all other limits are at T
A
= 25°C, unless otherwise specified.
Units
Symbol Parameter Conditions
(1)
Typical
(2)
Limits
(1)(2)
(Limits)
400h to C00h code change
t
s
Output Voltage Settling Time
(3)
6 8.5 µs (max)
R
L
= 2kΩ, C
L
= 200 pF
SR Output Slew Rate 1 V/µs
Glitch Impulse Code change from 800h to 7FFh 12 nV-sec
Digital Feedthrough 0.5 nV-sec
Multiplying Bandwidth
(4)
V
REF
= 2.5V ± 0.1Vpp 160 kHz
V
REF
= 2.5V ± 0.1Vpp
Total Harmonic Distortion
(4)
70 dB
input frequency = 10kHz
V
A
= 3V 0.8 µsec
t
WU
Wake-Up Time
V
A
= 5V 0.5 µsec
DIGITAL TIMING SPECS (SCL, SDA)
Standard Mode 100 kHz (max)
Fast Mode 400 kHz (max)
f
SCL
Serial Clock Frequency
High Speed Mode, C
b
= 100pF 3.4 MHz (max)
High Speed Mode, C
b
= 400pF 1.7 MHz (max)
Standard Mode 4.7 µs (min)
Fast Mode 1.3 µs (min)
t
LOW
SCL Low Time
High Speed Mode, C
b
= 100pF 160 ns (min)
High Speed Mode, C
b
= 400pF 320 ns (min)
Standard Mode 4.0 µs (min)
Fast Mode 0.6 µs (min)
t
HIGH
SCL High Time
High Speed Mode, C
b
= 100pF 60 ns (min)
High Speed Mode, C
b
= 400pF 120 ns (min)
Standard Mode 250 ns (min)
t
SU;DAT
Data Setup Time Fast Mode 100 ns (min)
High Speed Mode 10 ns (min)
(1) C
b
refers to the capacitance of one bus line. C
b
is expressed in pF units.
(2) Typical figures are at T
J
= 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing
Quality Level).
(3) This parameter is specified by design and/or characterization and is not tested in production.
(4) Applies to the Multiplying DAC configuration. In this configuration, the reference is used as the analog input. The value loaded in the
DAC Register will digitally attenuate the signal at Vout.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: DAC121C081 DAC121C085