Datasheet

Snap
Back
GND
D1
PIN
V+
2.1k
41.5k
41.5k
Snap
Back
GND
D1
PIN
DAC121C081, DAC121C085
www.ti.com SNAS395D –DECEMBER 2007–REVISED MARCH 2013
PIN DESCRIPTIONS
Symbol Type Equivalent Circuit Description
V
OUT
Analog Output Analog Output Voltage.
Power supply input. For the SOT and WSON versions, this
V
A
Supply
supply is used as the reference. Must be decoupled to GND.
GND Ground Ground for all on-chip circuitry.
Serial Data bi-directional connection. Data is clocked into or
Digital out of the internal 16-bit register relative to the clock edges
SDA
Input/Output of SCL. This is an open drain data line that must be pulled
to the supply (V
A
) by an external pull-up resistor.
Serial Clock Input. SCL is used together with SDA to control
SCL Digital Input
the transfer of data in and out of the device.
Tri-state Address Selection Input. Sets the two Least
Digital Input,
ADR0 Significant Bits (A1 & A0) of the 7-bit slave address. (see
three levels
Table 1)
Digital Input, Tri-state Address Selection Input. Sets Bits A6 & A3 of the
ADR1
three levels 7-bit slave address. (see Table 1)
Unbufferred reference voltage. For the VSSOP, this supply
V
REF
Supply is used as the reference. V
REF
must be free of noise and
decoupled to GND.
Exposed die attach pad can be connected to ground or left
PAD floating. Soldering the pad to the PCB offers optimal thermal
Ground
(LLP only) performance and enhances package self-alignment during
reflow.
Package Pinouts
V
OUT
V
A
GND SDA SCL ADR0 ADR1 V
REF
PAD (WSON only)
SOT 1 2 3 4 5 6 N/A N/A N/A
WSON 6 5 4 3 2 1 N/A N/A 7
VSSOP 8 6 5 4 3 1 2 7 N/A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DAC121C081 DAC121C085