Datasheet

1 9 1 9
Start by
Master
R/W
Frame 1
Address Byte
from Master
D7 D6 D5 D4 D3 D2 D1 D0
1 9
Frame 3
Data Byte from
Master
Stop by
Master
SCL
SDA
Frame 2
Data Byte from
Master
ACK
by
DAC121C081
ACK
by
DAC121C081
ACK
by
DAC121C081
A2 A0A1A3A4A5A6 0 0 PD1 PD0 D11 D10 D9 D8
Repeat Frames
2 & 3 for
Continuous Mode
DAC121C081, DAC121C085
SNAS395D –DECEMBER 2007–REVISED MARCH 2013 www.ti.com
Keep in mind that the address selection inputs (ADR0 and ADR1) are only sampled until the DAC is correctly
addressed with a non-broadcast address. At this point, the ADR0 and ADR1 inputs TRI-STATE and the slave
address is "locked". Changes to ADR0 and ADR1 will not update the selected slave address until the device is
power-cycled.
Table 1. Slave Addresses
DAC121C085 (VSSOP) DAC121C081 (SOT & WSON) *
Slave Address
[A6 - A0] ADR1 ADR0 ADR0
0001100 Floating Floating Floating
0001101 Floating GND GND
0001110 Floating V
A
V
A
0001000 GND Floating ---------------
0001001 GND GND ---------------
0001010 GND V
A
---------------
1001100 V
A
Floating ---------------
1001101 V
A
GND ---------------
1001110 V
A
V
A
---------------
1001000 --------------- Broadcast Address ---------------
* Pin-compatible alternatives to the DAC121C081 options are available with additional address options.
Writing to the DAC Register
To write to the DAC, the master addresses the part with the correct slave address (A6-A0) and writes a "zero" to
the read/write bit. If addressed correctly, the DAC returns an ACK to the master. The master then sends out the
upper data byte. The DAC responds by sending an ACK to the master. Next, the master sends the lower data
byte to the DAC. The DAC responds by sending an ACK again. At this point, the master either sends the upper
byte of the next data word to be converted by the DAC, generates a Stop condition to end communication, or
generates a Repeated Start condition to begin communication with another device on the bus. Until generating a
Stop condition, the master can continuously write the upper and lower data bytes to the DAC register. This
allows for a maximum DAC conversion rate of 188.9 kilo-conversions per second in Hs-mode.
Figure 23. Typical Write to the DAC Register
Reading from the DAC Register
To read from the DAC register, the master addresses the part with the correct slave address (A6-A0) and writes
a "one" to the read/write bit. If addressed correctly, the DAC returns an ACK to the master. Next, the DAC sends
out the upper data byte. The master responds by sending an ACK to the DAC to indicate that it wants to receive
another data byte. Then the DAC sends the lower data byte to the master. Assuming only one 16-bit data word is
read, the master sends a NACK after receiving the lower data byte. At this point, the master either generates a
Stop condition to end communication, or a Repeated Start condition to begin communication with another device
on the bus.
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