Datasheet

SCL
SDA
START or
REPEATED
START
STOP
1 2 6 7
8
9
1 2
8
9
MSB
7-bit Slave Address
R/W
Direction
Bit
Acknowledge
from the Device
MSB
Data Byte
*Acknowledge
or Not-ACK
ACK N/ACK
Repeated for the Lower Data Byte
and Additional Data Transfers
LSB LSB
*Note: In continuous mode, this bit must be an ACK from
the data receiver. Immediately preceding a STOP
condition, this bit must be a NACK from the master.
DAC121C081, DAC121C085
SNAS395D –DECEMBER 2007–REVISED MARCH 2013 www.ti.com
The DAC121C085 comes with an external reference supply pin (V
REF
). For the DAC121C085, it is important that
V
REF
be kept as clean as possible.
The Applications Information section describes a handful of ways to drive the reference appropriately. Refer to
the USING REFERENCES AS POWER SUPPLIES section for details.
SERIAL INTERFACE
The I
2
C-compatible interface operates in all three speed modes. Standard mode (100kHz) and Fast mode
(400kHz) are functionally the same and will be referred to as Standard-Fast mode in this document. High-Speed
mode (3.4MHz) is an extension of Standard-Fast mode and will be referred to as Hs-mode in this document. The
following diagrams describe the timing relationships of the clock (SCL) and data (SDA) signals. Pull-up resistors
or current sources are required on the SCL and SDA busses to pull them high when they are not being driven
low. A logic zero is transmitted by driving the output low. A logic high is transmitted by releasing the output and
allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus
capacitance and operating speed.
Basic I
2
C Protocol
The I
2
C interface is bi-directional and allows multiple devices to operate on the same bus. To facilitate this bus
configuration, each device has a unique hardware address which is referred to as the "slave address." To
communicate with a particular device on the bus, the controller (master) sends the slave address and listens for
a response from the slave. This response is referred to as an acknowledge bit. If a slave on the bus is addressed
correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a
device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs also occur
on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte
is successfully received. When the master is reading data, the master ACKs after every data byte is received to
let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after
the last data byte and creates a Stop condition on the bus.
All communication on the bus begins with either a Start condition or a Repeated Start condition. The protocol for
starting the bus varies between Standard-Fast mode and Hs-mode. In Standard-Fast mode, the master
generates a Start condition by driving SDA from high to low while SCL is high. In Hs-mode, starting the bus is
more complicated. Please refer to the High-Speed (Hs) Mode section for the full details of a Hs-mode Start
condition. A Repeated Start is generated to either address a different device, or switch between read and write
modes. The master generates a Repeated Start condition by driving SDA low while SCL is high. Following the
Repeated Start, the master sends out the slave address and a read/write bit as shown in Figure 21. The bus
continues to operate in the same speed mode as before the Repeated Start condition.
All communication on the bus ends with a Stop condition. In either Standard-Fast mode or Hs-Mode, a Stop
condition occurs when SDA is pulled from low to high while SCL is high. After a Stop condition, the bus remains
idle until a master generates a Start condition.
Please refer to the Phillips I
2
C
®
Specification (Version 2.1 Jan, 2000) for a detailed description of the serial
interface.
Figure 21. Basic Operation.
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