Datasheet

DAC 3
D
IN1
SYNC
DAC 2 DAC 1
DAC 3 DAC 2
DAC 3
D
IN2
/D
OUT1
D
IN3
/D
OUT2
Data Loaded into the DACs
48 SCLK Cycles (16 X 3)
15
th
SCLK Cycle 31
st
SCLK Cycle
DAC 1
SCLK
D
IN
SYNC
D
OUT
DAC 2
SCLK
D
IN
SYNC
D
OUT
DAC 3
SCLK
D
IN
SYNC
D
OUT
SCLK
D
IN
SYNC
DAC108S085
SNAS423B –AUGUST 2007–REVISED MARCH 2013 www.ti.com
DAISY CHAIN OPERATION
Daisy chain operation allows communication with any number of DAC108S085s using a single serial interface.
As long as the correct number of data bits are input in a write sequence (multiple of sixteen bits), a rising edge of
SYNC will properly update all DACs in the system.
To support multiple devices in a daisy chain configuration, SCLK and SYNC are shared across all DAC108S085s
and D
OUT
of the first DAC in the chain is connected to D
IN
of the second. Figure 30 shows three DAC108S085s
connected in daisy chain fashion. Similar to a single channel write sequence, the conversion for a daisy chain
operation begins on a falling edge of SYNC and ends on a rising edge of SYNC. A valid write sequence for n
devices in a chain requires n times 16 falling edges to shift the entire input data stream through the chain. Daisy
chain operation is specifed for a maximum SCLK speed of 30MHz.
Figure 30. Daisy Chain Configuration
The serial data output pin, D
OUT
, is available on the DAC108S085 to allow daisy-chaining of multiple
DAC108S085 devices in a system. In a write sequence, D
OUT
remains low for the first fourteen falling edges of
SCLK before going high on the fifteenth falling edge. Subsequently, the next sixteen falling edges of SCLK will
output the first sixteen data bits entered into D
IN
. Figure 31 shows the timing of three DAC108S085s in
Figure 30. In this instance, It takes forty-eight falling edges of SCLK followed by a rising edge of SYNC to load all
three DAC108S085s with the appropriate register data. On the rising edge of SYNC, the programmed function is
executed in each DAC108S085 simultaneously.
Figure 31. Daisy Chain Timing Diagram
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