Datasheet

DB15 DB0
SCLK
D
IN
SYNC
t
SYNC
t
DS
t
DH
t
CL
t
CH
1 / f
SCLK
t
SH
|
|
||
1 2 13 14 15 16
t
SS
DAC108S085
www.ti.com SNAS423B –AUGUST 2007–REVISED MARCH 2013
A.C. and Timing Characteristics
The following specifications apply for V
A
= +2.7V to +5.5V, V
REF1,2
= V
A
, C
L
= 200 pF to GND, f
SCLK
= 30 MHz, input code
range 12 to 1011. Boldface limits apply for T
MIN
≤ T
A
≤ T
MAX
and all other limits are at T
A
= 25°C, unless otherwise
specified.
Limits Units
Symbol Parameter Conductions Typical
(1)
(Limits)
f
SCLK
SCLK Frequency 40 30 MHz (max)
100h to 300h code change
t
s
Output Voltage Settling Time
(2)
4.5 6.0 µs (max)
R
L
= 2kΩ, C
L
= 200 pF
SR Output Slew Rate 1 V/µs
GI Glitch Impulse Code change from 200h to 1FFh 40 nV-sec
DF Digital Feedthrough 0.5 nV-sec
DC Digital Crosstalk 0.5 nV-sec
CROSS DAC-to-DAC Crosstalk 1 nV-sec
MBW Multiplying Bandwidth V
REF1,2
= 2.5V ± 2Vpp 360 kHz
ONSD Output Noise Spectral Density DAC Code = 200h, 10kHz 40 nV/sqrt(Hz)
ON Output Noise BW = 30kHz 14 µV
V
A
= 3V 3 µsec
t
WU
Wake-Up Time
V
A
= 5V 20 µsec
1/f
SCLK
SCLK Cycle Time 25 33 ns (min)
t
CH
SCLK High time 7 10 ns (min)
t
CL
SCLK Low Time 7 10 ns (min)
3 10 ns (min)
SYNC Set-up Time prior to SCLK
t
SS
Falling Edge
1 / f
SCLK
- 3 ns (max)
Data Set-Up Time prior to SCLK Falling
t
DS
1.0 2.5 ns (min)
Edge
Data Hold Time after SCLK Falling
t
DH
1.0 2.5 ns (min)
Edge
0 3 ns (min)
SYNC Hold Time after the 16th falling
t
SH
edge of SCLK
1 / f
SCLK
- 3 ns (max)
t
SYNC
SYNC High Time 5 15 ns (min)
(1) Test limits are specified to AOQL (Average Outgoing Quality Level).
(2) This parameter is specified by design and/or characterization and is not tested in production.
Timing Diagrams
Figure 1. Serial Timing Diagram
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