Datasheet

V
OUT
10 BIT DAC
REF
10
BUFFER
DAC
REGISTER
V
REF
V
REF
VOUT
R
R
R
R
R
S
0
S
1
S
2
S
2
n
S
2
n-1
S
2
n-2
DAC108S085
SNAS423B –AUGUST 2007–REVISED MARCH 2013 www.ti.com
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE
The DAC108S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor
strings that are followed by an output buffer. The reference voltages are externally applied at V
REF1
for DAC
channels A through D and V
REF2
for DAC channels E through H.
For simplicity, a single resistor string is shown in Figure 27. This string consists of 1024 equal valued resistors
with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register
determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight
binary with an ideal output voltage of:
V
OUTA,B,C,D
= V
REF1
x (D / 1024) (2)
V
OUTE,F,G,H
= V
REF2
x (D / 1024)
where
• D is the decimal equivalent of the binary code that is loaded into the DAC register (3)
D can take on any value between 0 and 1023. This configuration ensures that the DAC is monotonic.
Figure 27. DAC Resistor String
Since all eight DAC channels of the DAC108S085 can be controlled independently, each channel consists of a
DAC register and a 10-bit DAC. Figure 28 is a simple block diagram of an individual channel in the
DAC108S085. Depending on the mode of operation, data written into a DAC register causes the 10-bit DAC
output to be updated or an additional command is required to update the DAC output. Further description of the
modes of operation can be found in the Serial Interface description.
Figure 28. Single Channel Block Diagram
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