Datasheet
Table Of Contents

POWER-ON
RESET
DAC
REGISTER
INPUT
CONTROL
LOGIC
10
POWER-DOWN
CONTROL
LOGIC
V
REFIN
DAC104S085
V
OUTA
10 BIT DAC
REF
10
SCLK
D
IN
SYNC
BUFFER
BUFFER
BUFFER
BUFFER
10
10
10
V
OUTB
V
OUTC
V
OUTD
2.5k 100k
2.5k 100k
2.5k 100k
2.5k 100k
10 BIT DAC
REF
10 BIT DAC
REF
10 BIT DAC
REF
V
A
V
OUTA
V
OUTB
V
OUTD
V
OUTC
SCLK
D
IN
V
REFIN
GND
1
2
3
4
5
10
9
8
7
6
SYNC
VSSOP
V
A
V
OUTA
V
OUTB
V
OUTD
V
OUTC
SCLK
D
IN
V
REFIN
GND
SON
1
2
3
4
5
10
9
8
7
6
SYNC
DAC104S085
SNAS362F –MAY 2006–REVISED MARCH 2013
www.ti.com
Pin Configuration
Block Diagram
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