Datasheet

68HC11
DAC101S101
PC7
SCK
MOSI
SCLK
DIN
SYNC
80C51/80L51
DAC101S101
P3.3
TXD
RXD
SCLK
DIN
SYNC
ADSP-2101/
ADSP2103
DAC101S101
TFS
DT
SCLK
DIN
SCLK
SYNC
DAC101S101, DAC101S101-Q1
SNAS321F –JUNE 2005–REVISED MARCH 2013 www.ti.com
Applications Information
The simplicity of the DAC101S101 implies ease of use. However, it is important to recognize that any data
converter that utilizes its supply voltage as its reference voltage will have essentially zero PSRR (Power Supply
Rejection Ratio). Therefore, it is necessary to provide a noise-free supply voltage to the device.
DSP/Microprocessor Interfacing
Interfacing the DAC101S101 to microprocessors and DSPs is quite simple. The following guidelines are offered
to hasten the design process.
ADSP-2101/ADSP2103 Interfacing
Figure 39 shows a serial interface between the DAC101S101 and the ADSP-2101/ADSP2103. The DSP should
be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control
register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
Figure 39. ADSP-2101/2103 Interface
80C51/80L51 Interface
A serial interface between the DAC101S101 and the 80C51/80L51 microcontroller is shown in Figure 40. The
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line
P3.3. This line is taken low when data is to transmitted to the DAC101S101. Since the 80C51/80L51 transmits 8-
bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must
be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of
data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the
80C51/80L51 transmits data with the LSB first while the DAC101S101 requires data with the MSB first.
Figure 40. 80C51/80L51 Interface
68HC11 Interface
A serial interface between the DAC101S101 and the 68HC11 microcontroller is shown in Figure 41. The SYNC
line of the DAC101S101 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.
The 68HC11 should be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the
second byte of data to the DAC, after which PC7 should be raised to end the write sequence.
Figure 41. 68HC11 Interface
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