Datasheet

MSB
X X PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0
DATA BITS
0 0 Normal Operation.
0 1 2.5 kÖ to GND.
1 0 100 kÖ to GND.
1 1 High Impedance.
LSB
Power-Down Modes
DAC101C081, DAC101C081Q, DAC101C085
SNVS801A –APRIL 2012–REVISED MARCH 2013 www.ti.com
Figure 28. DAC Register Contents
POWER-ON RESET
The power-on reset circuit controls the output voltage of the DAC during power-up. Upon application of power,
the DAC register is filled with zeros and the output voltage is 0 Volts. The output remains at 0V until a valid write
sequence is made to the DAC.
When resetting the device, it is crutial that the V
A
supply be lowered to a maximum of 200mV before the supply
is raised again to power-up the device. Dropping the supply to within 200mV of GND during a reset will ensure
the ADC performs as specified.
SIMULTANEOUS RESET
The broadcast address allows the I
2
C™ master to write a single word to multiple DACs simultaneously. Provided
that all of the DACs exist on a single I
2
C™ bus, every DAC will update when the broadcast address is used to
address the bus. This feature allows the master to reset all of the DACs on a shared I
2
C™ bus to a specific
digital code. For instance, if the master writes a power-down code to the bus with the broadcast address, all of
the DACs will power-down simultaneously.
POWER-DOWN MODES
The DAC101C081 has three power-down modes. In power-down mode, the supply current drops to 0.13µA at 3V
and 0.15µA at 5V (typ). The DAC101C081 is put into power-down mode by writing a one to PD1 and/or PD0.
The outputs can be set to high impedance, terminated by 2.5 kΩ to GND, or terminated by 100 kΩ to GND (see
Figure 28).
The bias generator, output amplifier, resistor string, and other linear circuitry are all shut down in any of the
power-down modes. When the DAC101C081 is powered down, the value written to the DAC register, including
the power-down bits, is saved. While the DAC is in power-down, the saved DAC register contents can be read
back. When the DAC is brought out of power-down mode, the DAC register contents will be overwritten and V
OUT
will be updated with the new 10-bit data value.
The time to exit power-down (Wake-Up Time) is typically 0.8µsec at 3V and 0.5µsec at 5V.
ADDITIONAL TIMING INFORMATION: t
outz
The t
outz
specification is provided to aid the design of the I
2
C bus. After the SCL bus is driven low by the I
2
C™
master, the SDA bus will be held for a short time by the DAC101C081. This time is referred to as t
outz
. The
following figure illustrates the relationship between the fall of SCL, at the 30% threshold, to the time when the
DAC begins to transition the SDA bus. The t
outz
specification only applies when the DAC is in control of the SDA
bus. The DAC is only in control of the bus during an ACK by the DAC101C081 or a data byte read from the DAC
(see Figure 27).
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