Datasheet

POWER-ON
RESET
DAC
REGISTER
I
2
C
INTERFACE
POWER-DOWN
CONTROL
LOGIC
V
REF
*
DAC101C081 / DAC101C085
SCL SDA
BUFFER
10
V
OUT
2.5k 100k
10 BIT DAC
GND
10
ADR1*
REF
ADR0
* NOTE: ADR1 and V
REF
are for the DAC101C085 only. The DAC101C085 uses an external
reference (V
REF
), whereas, the DAC101C081 uses the supply (V
A
) as the reference.
V
A
*
ADR1
SDA
ADR0
V
A
GND
VSSOP
1
2
4
7
8
3SCL 6
5
V
REF
V
OUT
DAC101C085
ADR0
SCL
SDA
V
OUT
V
A
GND
WSON
1
2
3
5
4
6
DAC101C081
ADR0
SCL
SDA
V
OUT
V
A
GND
SOT
1
2
3
5
4
6
DAC101C081
DAC101C081, DAC101C081Q, DAC101C085
SNVS801A –APRIL 2012–REVISED MARCH 2013 www.ti.com
Table 1. Pin-Compatible Alternatives
(1)
Resolution SOT-6 and WSON-6 Packages VSSOP-8 Package w/ External Reference
12-bit DAC121C081 DAC121C085
10-bit DAC101C081 DAC101C085
8-bit DAC081C081 DAC081C085
(1) All devices are fully pin and function compatible.
Connection Diagrams
Figure 1. 6-Lead WSON Package Figure 2. 6-Lead SOT Package Figure 3. 8-Lead VSSOP Package
See Package Number NGF0006A See Package Number DDC0006A See Package Number DGK0008A
Block Diagram
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