Datasheet
D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
ACK
by
DAC101C081
Start by
Master
NACK
by
Master
SCL
SDA
Stop by
Master
1 9
0 0 PD1 PD0 D11 D10 D9 D8
ACK
by
Master
Frame 1
Address Byte
from Master
Frame 2
Data Byte from
DAC101C081
Frame 3
Data Byte from
DAC101C081
R/W
A2 A0A1A3A4A5A6
1 9 1 9
Start by
Master
R/W
Frame 1
Address Byte
from Master
D7 D6 D5 D4 D3 D2 D1 D0
1 9
Frame 3
Data Byte from
Master
Stop by
Master
SCL
SDA
Frame 2
Data Byte from
Master
ACK
by
DAC101C081
ACK
by
DAC101C081
ACK
by
DAC101C081
A2 A0A1A3A4A5A6 0 0 PD1 PD0 D11 D10 D9 D8
Repeat Frames
2 and 3 for
Continuous Mode
DAC101C081, DAC101C081Q, DAC101C085
www.ti.com
SNVS801A –APRIL 2012–REVISED MARCH 2013
Writing to the DAC Register
To write to the DAC, the master addresses the part with the correct slave address (A6-A0) and writes a "zero" to
the read/write bit. If addressed correctly, the DAC returns an ACK to the master. The master then sends out the
upper data byte. The DAC responds by sending an ACK to the master. Next, the master sends the lower data
byte to the DAC. The DAC responds by sending an ACK again. At this point, the master either sends the upper
byte of the next data word to be converted by the DAC, generates a Stop condition to end communication, or
generates a Repeated Start condition to begin communication with another device on the bus. Until generating a
Stop condition, the master can continuously write the upper and lower data bytes to the DAC register. This
allows for a maximum DAC conversion rate of 188.9 kilo-conversions per second in Hs-mode.
Figure 26. Typical Write to the DAC Register
Reading from the DAC Register
To read from the DAC register, the master addresses the part with the correct slave address (A6-A0) and writes
a "one" to the read/write bit. If addressed correctly, the DAC returns an ACK to the master. Next, the DAC sends
out the upper data byte. The master responds by sending an ACK to the DAC to indicate that it wants to receive
another data byte. Then the DAC sends the lower data byte to the master. Assuming only one 16-bit data word is
read, the master sends a NACK after receiving the lower data byte. At this point, the master either generates a
Stop condition to end communication, or a Repeated Start condition to begin communication with another device
on the bus.
Figure 27. Typical Read from the DAC Register
DAC REGISTER
The DAC register, Figure 28, has sixteen bits. The first two bits are always zero. The next two bits determine the
mode of operation (normal mode or one of three power-down modes). The final twelve bits of the shift register
are the data bits. The data format is straight binary (MSB first, LSB last), with twelve 0's corresponding to an
output of 0V and twelve 1's corresponding to a full-scale output of V
A
- 1 LSB. When writing to the DAC Register,
V
OUT
will update on the rising edge of the ACK following the lower data byte.
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