Datasheet

SCL
SDA
START or
REPEATED
START
STOP
1 2 6 7
8
9
1 2
8
9
MSB
7-bit Slave Address
R/W
Direction
Bit
Acknowledge
from the Device
MSB
Data Byte
*Acknowledge
or Not-ACK
ACK N/ACK
Repeated for the Lower Data Byte
and Additional Data Transfers
LSB LSB
*Note: In continuous mode, this bit must be an ACK from
the data receiver. Immediately preceding a STOP
condition, this bit must be a NACK from the master.
DAC101C081, DAC101C081Q, DAC101C085
www.ti.com SNVS801A –APRIL 2012–REVISED MARCH 2013
Figure 24. Basic Operation.
Standard-Fast Mode
In Standard-Fast mode, the master generates a start condition by driving SDA from high to low while SCL is
high. The Start condition is always followed by a 7-bit slave address and a Read/Write bit. After these eight bits
have been transmitted by the master, SDA is released by the master and the DAC101C081 either ACKs or
NACKs the address. If the slave address matches, the DAC101C081 ACKs the master. If the address doesn't
match, the DAC101C081 NACKs the master.
For a write operation, the master follows the ACK by sending the upper eight data bits to the DAC101C081.
Then the DAC101C081 ACKs the transfer by driving SDA low. Next, the lower eight data bits are sent by the
master. The DAC101C081 then ACKs the transfer. At this point, the DAC output updates to reflect the contents
of the 16-bit DAC register. Next, the master either sends another pair of data bytes, generates a Stop condition
to end communication, or generates a Repeated Start condition to communicate with another device on the bus.
For a read operation, the DAC101C081 sends out the upper eight data bits of the DAC register. This is followed
by an ACK by the master. Next, the lower eight data bits of the DAC register are sent to the master. The master
then produces a NACK by letting SDA be pulled high. The NACK is followed by a master-generated Stop
condition to end communication on the bus, or a Repeated Start to communicate with another device on the bus.
High-Speed (Hs) Mode
For Hs-mode, the sequence of events to begin communication differ slightly from Standard-Fast mode. Figure 25
describes this in further detail. Initially, the bus begins running in Standard-Fast mode. The master generates a
Start condition and sends the 8-bit Hs master code (00001XXX) to the DAC101C081. Next, the DAC101C081
responds with a NACK. Once the SCL line has been pulled to a high level, the master switches to Hs-mode by
increasing the bus speed and generating a Repeated Start condition (driving SDA low while SCL is pulled high).
At this point, the master sends the slave address to the DAC101C081, and communication continues as shown
above in the "Basic Operation" Diagram (see Figure 24).
When the master generates a Repeated Start condition while in Hs-mode, the bus stays in Hs-mode awaiting the
slave address from the master. The bus continues to run in Hs-mode until a Stop condition is generated by the
master. When the master generates a Stop condition on the bus, the bus must be started in Standard-Fast mode
again before increasing the bus speed and switching to Hs-mode.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: DAC101C081 DAC101C081Q DAC101C085