Datasheet

DAC088S085
www.ti.com SNAS424C –AUGUST 2007–REVISED MARCH 2013
Table 3. Special Command Operations
DB[15:12] DB[11:0] Description of Mode
1 0 1 0 X X X X H G F E D C B A Update Select: The DAC outputs of the channels selected with a "1" in
DB[7:0] are updated simultaneously to the values in their respective control
registers.
1 0 1 1 D11 D10 ... D4 X X X X Channel A Write: Channel A's control register and DAC output are updated to
the data in DB[11:0]. The outputs of the other seven channels are also
updated according to their respective control register values.
1 1 0 0 D11 D10 ... D4 X X X X Broadcast: The data in DB[11:0] is written to all channels' control register and
DAC output simultaneously.
POWER-ON RESET
The power-on reset circuit controls the output voltages of the eight DACs during power-up. Upon application of
power, the DAC registers are filled with zeros and the output voltages are set to 0V. The outputs remain at 0V
until a valid write sequence is made.
POWER-DOWN MODES
The DAC088S085 has three power-down modes where different output terminations can be selected (see
Table 4). With all channels powered down, the supply current drops to 0.1 µA at 3V and 0.2 µA at 5V. By
selecting the channels to be powered down in DB[7:0] with a "1", individual channels can be powered down
separately or multiple channels can be powered down simultaneously. The three different output terminations
include high output impedance, 100k ohm to ground, and 2.5k ohm to ground.
The output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the power-down
modes. The bias generator, however, is only shut down if all the channels are placed in power-down mode. The
contents of the DAC registers are unaffected when in power-down. Therefore, each DAC register maintains its
value prior to the DAC088S085 being powered down unless it is changed during the write sequence which
instructed it to recover from power down. Minimum power consumption is achieved in the power-down mode with
SYNC idled high, D
IN
idled low, and SCLK disabled. The time to exit power-down (Wake-Up Time) is typically 3
µsec at 3V and 20 µsec at 5V.
Table 4. Power-Down Modes
DB[15:12] DB[11:8] 7 6 5 4 3 2 1 0 Output Impedance
1 1 0 1 X X X X H G F E D C B A High-Z outputs
1 1 1 0 X X X X H G F E D C B A 100 kΩ outputs
1 1 1 1 X X X X H G F E D C B A 2.5 kΩ outputs
Applications Information
EXAMPLES PROGRAMMING THE DAC088S085
This section will present the step-by-step instructions for programming the serial input register.
Updating DAC Outputs Simultaneously
When the DAC088S085 is first powered on, the DAC is operating in Write Register Mode (WRM). Operating in
WRM allows the user to program the registers of multiple DAC channels without causing the DAC outputs to be
updated. As an example, here are the steps for setting Channel A to a full scale output, Channel B to three-
quarters full scale, Channel C to half-scale, Channel D to one-quarter full scale and having all the DAC outputs
update simultaneously.
As stated previously, the DAC088S085 powers up in WRM. If the device was previously operating in Write
Through Mode (WTM), an extra step to set the DAC into WRM would be required. First, the DAC registers need
to be programmed to the desired values. To set Channel A to an output of full scale, write "0FF0" to the control
register. This will update the data register for Channel A without updating the output of Channel A. Second, set
Channel B to an output of three-quarters full scale by writing "1C00" to the control register. This will update the
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