Datasheet

POWER-ON
RESET
DAC
REGISTER
INPUT
CONTROL
LOGIC
8
POWER-DOWN
CONTROL
LOGIC
V
REFIN
DAC082S085
V
OUTA
8 BIT DAC
REF
8
SCLK
D
IN
SYNC
BUFFER
BUFFER
8
V
OUTB
2.5k 100k
2.5k 100k
8 BIT DAC
REF
DAC082S085
SNAS365F –MAY 2006–REVISED MARCH 2013 www.ti.com
Block Diagram
PIN DESCRIPTIONS
SON
VSSOP Symbol Type Description
Pin No.
1 V
A
Supply Power supply input. Must be decoupled to GND.
2 V
OUTA
Analog Output Channel A Analog Output Voltage.
3 V
OUTB
Analog Output Channel B Analog Output Voltage.
4 NC Not Connected
5 NC Not Connected
6 GND Ground Ground reference for all on-chip circuitry.
Unbuffered reference voltage shared by all channels. Must be decoupled
7 V
REFIN
Analog Input
to GND.
Serial Data Input. Data is clocked into the 16-bit shift register on the
8 D
IN
Digital Input
falling edges of SCLK after the fall of SYNC.
Frame synchronization input for the data input. When this pin goes low, it
enables the input shift register and data is transferred on the falling edges
9 SYNC Digital Input of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is
brought high before the 16th clock, in which case the rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the
10 SCLK Digital Input
falling edges of this pin.
Exposed die attach pad can be connected to ground or left floating.
PAD
11 Ground Soldering the pad to the PCB offers optimal thermal performance and
(SON only)
enhances package self-alignment during reflow.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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