Datasheet

SCL
SDA
START
1 2 6 7
8
9
8-ELW0DVWHUFRGH³00001[[[´
Not-Acknowledge
from the Device
NACK
5
Standard-Fast Mode Hs-Mode
Repeated
START
1 2
MSB
7-bit Slave
Address
DAC081C081, DAC081C085
SNAS449D –FEBRUARY 2008–REVISED MARCH 2013 www.ti.com
Standard-Fast Mode
In Standard-Fast mode, the master generates a start condition by driving SDA from high to low while SCL is
high. The Start condition is always followed by a 7-bit slave address and a Read/Write bit. After these eight bits
have been transmitted by the master, SDA is released by the master and the DAC081C081 either ACKs or
NACKs the address. If the slave address matches, the DAC081C081 ACKs the master. If the address doesn't
match, the DAC081C081 NACKs the master.
For a write operation, the master follows the ACK by sending the upper eight data bits to the DAC081C081.
Then the DAC081C081 ACKs the transfer by driving SDA low. Next, the lower eight data bits are sent by the
master. The DAC081C081 then ACKs the transfer. At this point, the DAC output updates to reflect the contents
of the 16-bit DAC register. Next, the master either sends another pair of data bytes, generates a Stop condition
to end communication, or generates a Repeated Start condition to communicate with another device on the bus.
For a read operation, the DAC081C081 sends out the upper eight data bits of the DAC register. This is followed
by an ACK by the master. Next, the lower eight data bits of the DAC register are sent to the master. The master
then produces a NACK by letting SDA be pulled high. The NACK is followed by a master-generated Stop
condition to end communication on the bus, or a Repeated Start to communicate with another device on the bus.
High-Speed (Hs) Mode
For Hs-mode, the sequence of events to begin communication differ slightly from Standard-Fast mode. Figure 22
describes this in further detail. Initially, the bus begins running in Standard-Fast mode. The master generates a
Start condition and sends the 8-bit Hs master code (00001XXX) to the DAC081C081. Next, the DAC081C081
responds with a NACK. Once the SCL line has been pulled to a high level, the master switches to Hs-mode by
increasing the bus speed and generating a Repeated Start condition (driving SDA low while SCL is pulled high).
At this point, the master sends the slave address to the DAC081C081, and communication continues as shown
above in the "Basic Operation" Diagram (see Figure 21).
When the master generates a Repeated Start condition while in Hs-mode, the bus stays in Hs-mode awaiting the
slave address from the master. The bus continues to run in Hs-mode until a Stop condition is generated by the
master. When the master generates a Stop condition on the bus, the bus must be started in Standard-Fast mode
again before increasing the bus speed and switching to Hs-mode.
Figure 22. Beginning Hs-Mode Communication
I
2
C Slave (Hardware) Address
The DAC has a seven-bit I
2
C slave address. For the VSSOP-8 version of the DAC, this address is configured by
the ADR0 and ADR1 address selection inputs. For the DAC081C081, the address is configured by the ADR0
address selection input. ADR0 and ADR1 can be grounded, left floating, or tied to V
A
. If desired, the address
selection inputs can be set to V
A
/2 rather than left floating. The state of these inputs sets the address the DAC
responds to on the I
2
C bus (see Table 1). In addition to the selectable slave address, there is also a broadcast
address (1001000) for all DAC081C081's and DAC081C085's on the 2-wire bus. When the bus is addressed by
the broadcast address, all the DAC081C081's and DAC081C085's will respond and update synchronously.
Figure 23 and Figure 24 describe how the master device should address the DAC via the I
2
C-Compatible
interface.
16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085