Datasheet

SCL
SDA
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
SP
t
r
t
BUF
OUTPUT
VOLTAGE
DIGITAL INPUT CODE
0
0 255
ZE
FSE
GE = FSE - ZE
FSE = GE + ZE
255 x V
REF
256
DAC081C081, DAC081C085
SNAS449D –FEBRUARY 2008–REVISED MARCH 2013 www.ti.com
device without a load.
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is
updated.
TOTAL HARMONIC DISTORTION (THD)is the measure of the harmonics present at the output of the DACs
with an ideal sine wave applied to V
REFIN
. THD is measured in dB.
WAKE-UP TIME is the time for the output to exit power-down mode. This time is measured from the rising edge
of SCL during the ACK bit of the lower data byte to the time the output voltage deviates from the power-
down voltage of 0V.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been
entered.
Transfer Characteristic
Figure 1. Input / Output Transfer Characteristic
Timing Diagrams
Figure 2. Serial Timing Diagram
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