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DAC081C081, DAC081C085

www.ti.com

SNAS449D –FEBRUARY 2008–REVISED MARCH 2013

DAC081C081/ DAC081C085 8-Bit Micro Power Digital-to-Analog Converter with an I

C-

Compatible Interface

Check for Samples: DAC081C081, DAC081C085

FEATURES

DESCRIPTION

The DAC081C081 is an 8-bit, single channel, voltage-

• Ensured Monotonicity to 8-bits

output digital-to-analog converter (DAC) that operates

• Low Power Operation: 156 µA Max @ 3.3V

from a +2.7V to 5.5V supply. The output amplifier

• Extended Power Supply Range (+2.7V to

allows rail-to-rail output swing and has an 4.5µsec

+5.5V)

settling time. The DAC081C081 uses the supply

voltage as the reference to provide the widest

• I

C-Compatible 2-Wire Interface which

dynamic output range and typically consumes 132µA

Supports Standard (100kHz), fast (400kHz),

while operating at 5.0V. It is available in 6-lead SOT

and High Speed (3.4MHz) Modes

and WSON packages and provides three address

• Rail-to-Rail Voltage Output

options (pin selectable).

• Very Small Package

As an alternative, the DAC081C085 provides nine I

APPLICATIONS

addressing options and uses an external reference. It

has the same performance and settling time as the

• Industrial Process Control

DAC081C081. It is available in an 8-lead VSSOP.

• Portable Instruments

The DAC081C081 and DAC081C085 use a 2-wire,

• Digital Gain and Offset Adjustment

C-compatible serial interface that operates in all

• Programmable Voltage & Current Sources

three speed modes, including high speed mode

• Test Equipment

(3.4MHz). An external address selection pin allows up

to three DAC081C081 or nine DAC081C085 devices

KEY SPECIFICATIONS

per 2-wire bus. Pin compatible alternatives to the

DAC081C081 are available that provide additional

• Resolution 8 bits

address options.

• INL ±0.6 LSB (max)

The DAC081C081 and DAC081C085 each have a

• DNL ±0.1 LSB (max)

16-bit register that controls the mode of operation, the

• Settling Time 4.5 μs (max)

power-down condition, and the output voltage. A

power-on reset circuit ensures that the DAC output

• Zero Code Error +10 mV (max)

powers up to zero volts. A power-down feature

• Full-Scale Error −0.7 %FS (max)

reduces power consumption to less than a microWatt.

• Supply Power

Their low power consumption and small packages

make these DACs an excellent choice for use in

– Normal

battery operated equipment. Each DAC operates over

– 380 μW (3V)

the extended industrial temperature range of −40°C

– 730 μW (5V) typ

to +125°C.

– Power Down

The DAC081C081 and DAC081C085 are each part of

– 0.5 μW (3V)

a family of pin compatible DACs that also provide 12

and 10 bit resolution. For 12-bit DACs see the

– 0.9 μW (5V) typ

DAC121C081 and DAC121C085. For 10-bit DACs

see the DAC101C081 and DAC101C085.

Pin-Compatible Alternatives

(1)

Resolution SOT-6 and WSON-6 VSSOP-8 Package w/

Packages External Reference

12-bit DAC121C081 DAC121C085

10-bit DAC101C081 DAC101C085

(1) All devices are fully pin and function compatible.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

PAGE 1
DAC081C081, DAC081C085 www.ti.com SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 DAC081C081/ DAC081C085 8-Bit Micro Power Digital-to-Analog Converter with an I2CCompatible Interface Check for Samples: DAC081C081, DAC081C085 FEATURES DESCRIPTION • • • The DAC081C081 is an 8-bit, single channel, voltageoutput digital-to-analog converter (DAC) that operates from a +2.7V to 5.5V supply. The output amplifier allows rail-to-rail output swing and has an 4.5µsec settling time.
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DAC081C081, DAC081C085 SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.
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DAC081C081, DAC081C085 www.ti.com SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 PIN DESCRIPTIONS (continued) Symbol ADR0 Type Equivalent Circuit Digital Input, three levels V+ PIN ADR1 Description Tri-state Address Selection Input. Sets the two Least Significant Bits (A1 & A0) of the 7-bit slave address. (see Table 1) Snap Back Digital Input, three levels 2.1k D1 41.5k Tri-state Address Selection Input. Sets Bits A6 & A3 of the 7-bit slave address. (see Table 1) 41.
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DAC081C081, DAC081C085 SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 Absolute Maximum Ratings www.ti.com (1) (2) (3) Supply Voltage, VA −0.3V to +6.5V Voltage on any Input Pin −0.3V to +6.
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DAC081C081, DAC081C085 www.ti.com SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 Package Thermal Resistances (1) (1) Package θJA 6-Lead SOT 250°C/W 6-Lead WSON 190°C/W 8-Lead VSSOP 240°C/W Soldering process must comply with Reflow Temperature Profile specifications. Refer to http://www.ti.com/packaging. Reflow temperature profiles are different for lead-free packages. Electrical Characteristics Values shown in this table are design targets and are subject to change before product release.
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DAC081C081, DAC081C085 SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, CL = 200 pF to GND, input code range 3 to 252. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
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DAC081C081, DAC081C085 www.ti.com SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 Electrical Characteristics (continued) Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, CL = 200 pF to GND, input code range 3 to 252. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
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DAC081C081, DAC081C085 SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com A.C. and Timing Characteristics (continued) Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, RL = Infinity, CL = 200 pF to GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Symbol tHD;DAT Limits (1) (2) Units (Limits) Standard Mode 0 3.
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DAC081C081, DAC081C085 www.ti.com SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 A.C. and Timing Characteristics (continued) Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, RL = Infinity, CL = 200 pF to GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Symbol Limits (1) (2) Units (Limits) 300 ns (max) 20+0.
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DAC081C081, DAC081C085 SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com device without a load. SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated. TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs with an ideal sine wave applied to VREFIN. THD is measured in dB. WAKE-UP TIME is the time for the output to exit power-down mode.
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DAC081C081, DAC081C085 www.ti.com SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 Typical Performance Characteristics VREF = VA, fSCL = 3.4MHz, TA = 25°C, Input Code Range 3 to 252, unless otherwise stated. INL DNL Figure 3. Figure 4. INL/DNL vs Temperature at VA = 3.0V INL/DNL vs Temperature at VA = 5.0V Figure 5. Figure 6. INL/DNL vs VREFIN at VA = 3.0V INL/DNL vs VREFIN at VA = 5.0V Figure 7. Figure 8.
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DAC081C081, DAC081C085 SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VREF = VA, fSCL = 3.4MHz, TA = 25°C, Input Code Range 3 to 252, unless otherwise stated. 12 INL/DNL vs VA Zero Code Error vs. VA Figure 9. Figure 10. Zero Code Error vs. Temperature Full Scale Error vs. VA Figure 11. Figure 12. Full Scale Error vs. Temperature Total Supply Current vs. VA Figure 13. Figure 14.
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DAC081C081, DAC081C085 www.ti.com SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VREF = VA, fSCL = 3.4MHz, TA = 25°C, Input Code Range 3 to 252, unless otherwise stated. VREF Supply Current vs. VA Total Supply Current vs. Temperature @ VA = 3V Figure 15. Figure 16. Total Supply Current vs. Temperature @ VA = 5V 5V Glitch Response Figure 17. Figure 18. Power-On Reset Figure 19.
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DAC081C081, DAC081C085 SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION DAC SECTION The DAC081C081 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer. For simplicity, a single resistor string is shown in Figure 20. This string consists of 256 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground.
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DAC081C081, DAC081C085 www.ti.com SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 SERIAL INTERFACE The I2C-compatible interface operates in all three speed modes. Standard mode (100kHz) and Fast mode (400kHz) are functionally the same and will be referred to as Standard-Fast mode in this document. High-Speed mode (3.4MHz) is an extension of Standard-Fast mode and will be referred to as Hs-mode in this document.
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DAC081C081, DAC081C085 SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Standard-Fast Mode In Standard-Fast mode, the master generates a start condition by driving SDA from high to low while SCL is high. The Start condition is always followed by a 7-bit slave address and a Read/Write bit. After these eight bits have been transmitted by the master, SDA is released by the master and the DAC081C081 either ACKs or NACKs the address. If the slave address matches, the DAC081C081 ACKs the master.
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DAC081C081, DAC081C085 www.ti.com SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 Keep in mind that the address selection inputs (ADR0 and ADR1) are only sampled until the DAC is correctly addressed with a non-broadcast address. At this point, the ADR0 and ADR1 inputs TRI-STATE and the slave address is "locked". Changes to ADR0 and ADR1 will not update the selected slave address until the device is power-cycled. Table 1.
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DAC081C081, DAC081C085 SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 1 www.ti.com 9 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W 0 ACK by DAC081C081 Start by Master Frame 1 Address Byte from Master 0 PD1 PD0 D11 D10 D9 D8 Frame 2 Data Byte from DAC081C081 D7 D6 D5 ACK by Master D4 D3 D2 Frame 3 Data Byte from DAC081C081 D1 D0 NACK by Master Stop by Master Figure 24. Typical Read from the DAC Register DAC REGISTER The DAC register, Figure 25, has sixteen bits.
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DAC081C081, DAC081C085 www.ti.com SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 ADDITIONAL TIMING INFORMATION: toutz The toutz specification is provided to aid the design of the I2C bus. After the SCL bus is driven low by the I2C master, the SDA bus will be held for a short time by the DAC081C081. This time is referred to as toutz. The following figure illustrates the relationship between the fall of SCL, at the 30% threshold, to the time when the DAC begins to transition the SDA bus.
PAGE 20
DAC081C081, DAC081C085 SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Input Voltage R IDAC VZ IZ 0.1 PF 0.47 PF VA VREF LM4050-4.1 or LM4050-5.0 DAC081C081/5 VOUT = 0V to 5V SDA SCL Figure 28. The LM4050 as a power supply The minimum resistor value in the circuit of Figure 28 must be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating.
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DAC081C081, DAC081C085 www.ti.com SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 VIN Input Voltage VOUT LP2980 1 PF ON /OFF 0.1 PF VA VREF DAC081C081/5 VOUT = 0V to 5V SDA SCL Figure 30. Using the LP2980 regulator Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance.
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DAC081C081, DAC081C085 SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com Table 2. Some Rail-to-Rail Amplifiers AMP PKGS LMP7701 SOT23-5 Typ VOS Typ ISUPPLY 37 uV 0.79 mA LMV841 SC70-5 50 uV 1 mA LMC7111 SOT23-5 0.9 mV 25 µA LM7301 SO-8 SOT23-5 0.03 mV 620 µA LM8261 SOT23-5 0.7 mV 1 mA DSP/MICROPROCESSOR INTERFACING Interfacing the DAC081C081 to microprocessors and DSPs is quite simple. The following guidelines are offered to simplify the design process.
PAGE 23
DAC081C081, DAC081C085 www.ti.com SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 LAYOUT, GROUNDING, AND BYPASSING For best accuracy and minimum noise, the printed circuit board containing the DAC081C081 should have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of these planes should be located on the same board layer. There should be a single ground plane.
PAGE 24
DAC081C081, DAC081C085 SNAS449D – FEBRUARY 2008 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision C (March 2013) to Revision D • 24 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC081C081CIMK/NOPB DAC081C081CIMKX/NOP B Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SOT DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC081C081CIMK/NOPB SOT DDC 6 1000 210.0 185.0 35.0 SOT DDC 6 3000 210.0 185.0 35.0 DAC081C081CIMKX/NOP B WSON NGF 6 1000 210.0 185.0 35.0 DAC081C081CISDX/NOP B DAC081C081CISD/NOPB WSON NGF 6 4500 367.0 367.0 35.0 DAC081C085CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 VSSOP DGK 8 3500 367.0 367.
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MECHANICAL DATA NGF0006A www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.