Datasheet

CY74FCT825T
8-BIT BUS-INTERFACE REGISTER
WITH 3-STATE OUTPUTS
SCCS070A – OCTOBER 2001 – REVISED NOVEMBER 2001
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PIN DESCRIPTION
NAME
I/O DESCRIPTION
D I D flip-flop data inputs
CLR I When CLR is low and OE is low, Q outputs are low. When CLR is high, data can be entered into the register.
CP O Clock pulse for the register. Enters data into the register on the low-to-high clock transition.
Y O Register 3-state outputs
EN
I
Clock enable. When EN is low, data on the D input is transferred to the Q output on the low-to-high clock transition. When
EN
is high, the Q outputs do not change state, regardless of the data or clock input transitions.
OE
I
Output control. When OE is high, the Y outputs are in the high-impedance state. When OE is low, true register data is present
at the Y outputs.
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
FUNCTION
OE CLR EN D CP Q Y
H H L L ↑ L Z
Z
H HLH↑ H Z
Z
H L X X X L Z
Clear
L LXXXLL
Clear
H H H X X NC Z
Hold
L HHXXNCNC
Hold
H H L L ↑ L Z
H HLH↑ H Z
Load
L HLL↑ L L
Load
L H L H ↑ H H
H = High logic level, L = Low logic level, X = Don’t care, NC = No change,
↑ = Low-to-high transition, Z = High-impedance state
logic diagram (positive logic)
Q
To Seven Other Channels
Y
0
EN
OE
2
CLR
11
13
14
3
CL
D
CP
22
OE
1
OE
3
23
2
1
CP
D
0