Datasheet

CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS031A – JULY 1994 – REVISED OCTOBER 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
CY54FCT646T CY74FCT646T
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP
†
MAX MIN TYP
†
MAX
UNIT
#
V55V
One bit
switching
at f
1
= 5 MHz
V
IN
≤ 0.2 V or
V
IN
≥ V
CC
– 0.2 V
0.7 1.4
#
V
CC
= 5.5 V,
f
0
= 10 MHz,
Out
p
uts o
p
en
1
at 50% duty
cycle
V
IN
= 3.4 V or GND 1.2 3.4
mA
#
Outputs
open
,
G
= DIR = GND,
SAB = SBA
= GND
Eight bits
switching
at f
1
= 5 MHz
V
IN
≤ 0.2 V or
V
IN
≥ V
CC
– 0.2 V
2.8 5.6
||
mA
I
C
#
1
at 50% duty
cycle
V
IN
= 3.4 V or GND 5.1 14.6
||
I
C
#
V 5 25 V
One bit
switching
at f
1
= 5 MHz
V
IN
≤ 0.2 V or
V
IN
≥ V
CC
– 0.2 V
0.7 1.4
V
CC
= 5.25 V,
f
0
= 10 MHz,
Out
p
uts o
p
en
1
at 50% duty
cycle
V
IN
= 3.4 V or GND 1.2 3.4
mA
Outputs
open
,
G
= DIR = GND,
SAB = SBA
= GND
Eight bits
switching
at f
1
= 5 MHz
V
IN
≤ 0.2 V or
V
IN
≥ V
CC
– 0.2 V
2.8 5.6
||
mA
1
at 50% duty
cycle
V
IN
= 3.4 V or GND 5.1 14.6
||
C
i
6 10 6 10 pF
C
o
8 12 8 12 pF
#
I
C
= I
CC
+ ∆I
CC
× D
H
× N
T
+ I
CCD
(f
0
/2 + f
1
× N
1
)
Where:
I
C
= Total supply current
I
CC
= Power-supply current with CMOS input levels
∆I
CC
= Power-supply current for a TTL high input (V
IN
= 3.4 V)
D
H
= Duty cycle for TTL inputs high
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic current caused by an input transition pair (HLH or LHL)
f
0
= Clock frequency for registered devices, otherwise zero
f
1
= Input signal frequency
N
1
= Number of inputs changing at f
1
All currents are in milliamperes and all frequencies are in megahertz.
||
Values for these conditions are examples of the I
CC
formula.