Datasheet

CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS031A – JULY 1994 – REVISED OCTOBER 2001
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PIN DESCRIPTION
NAME
DESCRIPTION
A Data register A inputs, data register B outputs
B Data register B inputs, data register A outputs
CPAB, CPBA Clock-pulse inputs
SAB, SBA Output data-source-select inputs
DIR, G Output-enable inputs
ORDERING INFORMATION
T
A
PACKAGE
†
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP – Q Tape and reel 5.4 CY74FCT646CTQCT FCT646C
SOIC SO
Tube 5.4 CY74FCT646CTSOC
FCT646C
SOIC
–
SO
Tape and reel 5.4 CY74FCT646CTSOCT
FCT646C
QSOP – Q Tape and reel 6.3 CY74FCT646ATQCT FCT646A
–40°C to 85°C
SOIC SO
Tube 6.3 CY74FCT646ATSOC
FCT646A
SOIC
–
SO
Tape and reel 6.3 CY74FCT646ATSOCT
FCT646A
QSOP – Q Tape and reel 9 CY74FCT646TQCT FCT646
SOIC SO
Tube 9 CY74FCT646TSOC
FCT646
SOIC
–
SO
Tape and reel 9 CY74FCT646TSOCT
FCT646
LCC – L Tube 6 CY54FCT646CTLMB
55°Cto125°C
CDIP – D Tube 7.7 CY54FCT646ATDMB
–
55°C
to
125°C
LCC L
Tube 7.7 CY54FCT646ATLMB
LCC
–
L
Tube 11 CY54FCT646TLMB
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
DATA I/O
‡
OPERATION
G DIR CPAB CPBA SAB SBA A
1
–A
8
B
1
–B
8
OR FUNCTION
H X H or L H or L X X Input Input Isolation
H X ↑↑X X Input Input Store A and B data
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus
H = High logic level, L = Low logic level, ↑ = Low-to-high transition, X = Don’t care
‡
The data output functions can be enabled or disabled by various signals at the G
or DIR inputs. Data input
functions always are enabled, i.e., data at the bus pins is stored on every low-to-high transition of the
clock inputs.