Datasheet

CY54FCT273T, CY74FCT273T
8-BIT REGISTERS
SCCS020A – MARCH 1995 – REVISED OCTOBER 2001
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION
T
A
PACKAGE
†
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP – Q Tape and reel 5.8 CY74FCT273CTQCT FCT273C
SOIC SO
Tube 5.8 CY74FCT273CTSOC
FCT273C
SOIC
–
SO
Tape and reel 5.8 CY74FCT273CTSOCT
FCT273C
QSOP – Q Tape and reel 7.2 CY74FCT273ATQCT FCT273A
–40°C to 85°C
SOIC SO
Tube 7.2 CY74FCT273ATSOC
FCT273A
SOIC
–
SO
Tape and reel 7.2 CY74FCT273ATSOCT
FCT273A
QSOP – Q Tape and reel 13 CY74FCT273TQCT FCT273
SOIC SO
Tube 13 CY74FCT273TSOC
FCT273
SOIC
–
SO
Tape and reel 13 CY74FCT273TSOCT
FCT273
–55°C to 125°C LCC – L Tube 8.3 CY54FCT273ATLMB
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUT OPERATING
MR CP D
Q MODE
L X X L Reset (clear)
H
↑
h H Load ‘1’
H
↑
l L Load ‘0’
H = High logic level steady state, h = High logic level one
setup time prior to low-to-high clock transition, L = Low
logic level steady state, l = Low logic level one setup time
prior to the low-to-high transition, X = Don’t care,
↑ = Low-to-high clock transition
logic diagram (positive logic)
CP
D
0
MR
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
3 4 7 8 13 14 17 18
2 5 6 9 12 15 16 19
11
1
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7