Using the CSD86330EVM-717 User's Guide Literature Number: SLUU480 February 2011
User's Guide SLUU480 – February 2011 Synchronous Buck NexFET Power Block 1 Introduction The CSD86330EVM-717 evaluation module (EVM) uses the CSD86330. The CSD86330 power block is an optimized design for synchronous buck applications offering high-current, high-efficiency, and high-frequency capability in a small 3.3-mm x 3.3-mm outline. CSD86330EVM-717 also uses TPS53219 as a small size single-buck controller with adaptive on-time D-CAP ™ mode control. The EVM provides a fixed 1.
Electrical Performance Specifications www.ti.com 3 Electrical Performance Specifications Table 1. CSD86330EVM-717 Electrical Performance Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Characteristics Voltage range VIN Maximum input current VIN = 9 V, IO = 10 A 9 No load input current VIN = 13.2 V, IO = 0 A 12 13.2 1.6 V A 1 mA Output Characteristics Output voltage VOUT IO = 5 A Output voltage regulation Line regulation(VIN = 9 V 13.2 V. IO=0 A - 10 A) 0.
Schematic Schematic + 4 www.ti.com Figure 1.
Test Setup www.ti.com 5 Test Setup 5.1 Test Equipment Voltage Source: The input voltage source VIN should be a 0-V to 13.2-V variable DC source capable of supplying 4 ADC. Connect VIN to board as shown in Figure 3. Multimeters: • V1: VIN at TP1 (VIN) and TP2 (GND). • V2: VOUT at TP5 (VOUT) and TP6 (GND). • A1: VIN input current. Output Load: The output load should be an electronic constant resistance mode load capable of 0 ADC to 10 ADC at 1.2 V.
Test Setup 5.2 www.ti.com Recommended Test Setup Figure 3 is the recommended test set up to evaluate the CSD86330EVM-717. Working at an ESD workstation, make sure that any wrist straps, bootstraps or mats are connected referencing the user to earth ground before power is applied to the EVM. Figure 3. CSD86330EVM-717 Recommended Test Set Up Input Connections: • Prior to connecting the DC input source VIN, it is advisable to limit the source current from VIN to 10 A maximum.
Test Procedure www.ti.com 6 Test Procedure 6.1 Line/Load Regulation and Efficiency Measurement Procedure 1. 2. 3. 4. 5. 6. 7. 8. 9. 6.2 Set up the EVM as described in Section 5 and Figure 3. Ensure load is set to constant resistance mode and to sink 0 ADC. Ensure all configuration settings are as per Section 6. Increase VIN from 0 V to 12 V. Using V1 to measure input voltage. Use V2 to measure VOUT voltage. Vary load from 0 ADC to 10 ADC, VOUT should remain in load regulation.
Performance Data and Typical Characteristic Curves 7 www.ti.com Performance Data and Typical Characteristic Curves Figure 4 through Figure 11 present typical performance curves for CSD86330EVM-717. 7.1 Efficiency EFFICIENCY vs LOAD CURRENT p – Efficiency - % 100 90 80 9.0 V 12.0 V 13.2 V 70 0.5 4.5 2.5 8.5 0.6 10.5 ILOAD – Load Current - A Figure 4. Efficiency 7.2 Light-Load Efficiency EFFICIENCY vs LOAD CURRENT 100 P – Efficiency - % 9.0 V 12.0 V 13.2 V 90 80 70 0.01 0.1 1.
Performance Data and Typical Characteristic Curves www.ti.com 7.3 Load Regulation OUTPUT VOLTAGE vs LOAD CURRENT 1.229 VOUT – Output Voltage - V 1.224 1.219 1.214 1.209 9.0 V 12.0 V 13.2 V 1.204 0 2 4 6 8 10 12 ILOAD – Load Current - A Figure 6. Load Regulation 7.4 Output Transient Figure 7.
Performance Data and Typical Characteristic Curves 7.5 www.ti.com Output Ripple Figure 8. Output Ripple 7.6 Switching Node Figure 9.
Performance Data and Typical Characteristic Curves www.ti.com 7.7 Thermal Image Figure 10. Top Board at 12 VIN, 1.2 V/10 A with natural air convection Figure 11. Bottom Board at 12 VIN, 1.
CSD86330EVM-717 Assembly Drawing and PCB Layout 8 www.ti.com CSD86330EVM-717 Assembly Drawing and PCB Layout The following figures (Figure 12 through Figure 19) show the design of the CSD86330EVM-717 printed circuit board. The EVM has been designed using six layers and a 2-oz copper circuit board. Figure 12. Top Layer Assembly Drawing (top view) Figure 13.
www.ti.com CSD86330EVM-717 Assembly Drawing and PCB Layout Figure 14. Top Copper Figure 15.
CSD86330EVM-717 Assembly Drawing and PCB Layout www.ti.com Figure 16. Layer 3 Figure 17.
www.ti.com CSD86330EVM-717 Assembly Drawing and PCB Layout Figure 18. Layer 5 Figure 19.
List of Materials 9 www.ti.com List of Materials The EVM components list according to Figure 1. Table 3. List of Materials QTY 16 REF DES DESCRIPTION MFR PART NUMBER 1 C1 Capacitor, ceramic, 25 V, X7R, 10%, 402 Std Std 2 C2, C14 Capacitor, ceramic, 25 V, X5R, 20%, 603 Std Std 3 C3, C4, C5 Capacitor, ceramic, 25 V, X5R, 20%, 1210 Std Std 2 C6 Capacitor, ceramic, 16 V, X7R, 10%, 402 Std Std 1 C7 Capacitor, POSCAP, 330 µF, 2.5 V, 0.
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