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8.4.5 Fast Interrupt Request Entry Address Register (FIQENTRY)
8.4.6 Interrupt Request Entry Address Register (IRQENTRY)
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The fast interrupt request entry address register (FIQENTRY) is shown in Figure 8-9 and described in
Table 8-7 . Entry address [28:0] for valid FIQ interrupt.
Figure 8-9. Fast Interrupt Request Entry Address Register (FIQENTRY)
31 29 28 16
Reserved FIQENTRY
R-0 R-0
15 0
FIQENTRY
R-0
LEGEND: R = Read only; - n = value after reset
Table 8-7. Fast Interrupt Request Entry Address Register (FIQENTRY) Field Descriptions
Bit Field Value Description
31-29 Reserved 0 Reserved
28-0 FIQENTRY 0-1FFF FFFFh Interrupt entry table address of the current highest-priority fast interrupt request (FIQ).
The interrupt request entry address register (IRQENTRY) is shown in Figure 8-10 and described in
Table 8-8 . Entry address [28:0] for valid IRQ interrupt.
Figure 8-10. Interrupt Request Entry Address Register (IRQENTRY)
31 29 28 16
Reserved IRQENTRY
R-0 R-0
15 0
IRQENTRY
R-0
LEGEND: R = Read only; - n = value after reset
Table 8-8. Interrupt Request Entry Address Register (IRQENTRY) Field Descriptions
Bit Field Value Description
31-29 Reserved 0 Reserved
28-0 IRQENTRY 0-1FFF FFFFh Interrupt entry table address of the current highest-priority interrupt request (IRQ).
ARM Interrupt Controller (AINTC)94 SPRUEP9A – May 2008
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