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8.4.1 Fast Interrupt Request Status Register 0 (FIQ0)
8.4.2 Fast Interrupt Request Status Register 1 (FIQ1)
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The fast interrupt request status register 0 (FIQ0) is shown in Figure 8-5 and described in Table 8-3 .
Interrupt status of INT[31:0] (if mapped to FIQ).
Figure 8-5. Fast Interrupt Request Status Register 0 (FIQ0)
31 16
FIQ
R/W-1
15 0
FIQ
R/W-1
LEGEND: R/W = Read/Write; - n = value after reset
Table 8-3. Fast Interrupt Request Status Register 0 (FIQ0) Field Descriptions
Bit Field Value Description
31-0 FIQ[ n] Interrupt status of INT n, if mapped to fast interrupt request (FIQ31-0).
0 When reading bit, interrupt occurred.
1 When writing bit, acknowledge interrupt.
The fast interrupt request status register 1 (FIQ1) is shown in Figure 8-6 and described in Table 8-4 .
Interrupt status of INT[63:32] (if mapped to FIQ).
Figure 8-6. Fast Interrupt Request Status Register 1 (FIQ1)
31 16
Reserved
R-1
15 0
FIQ
R/W-1
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-4. Fast Interrupt Request Status Register 1 (FIQ1) Field Descriptions
Bit Field Value Description
31-16 Reserved 1 Reserved
15-0 FIQ[ n] Interrupt status of INT n, if mapped to fast interrupt request (FIQ47-32).
0 When reading bit, interrupt occurred.
1 When writing bit, acknowledge interrupt.
ARM Interrupt Controller (AINTC)92 SPRUEP9A – May 2008
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