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8.3.4 Clearing Interrupts
8.3.5 Enabling and Disabling Interrupts
CLK
EABASE VECTORn
EABASE
VECTORn
INTn
EINTn
IRQn/FIQn
IRQz/FIQz
ENTRY
Eventpulse
Enabled
Disabled
Cleared
AINTC Methodology
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2. For the IRQENTRY:
• If IERAW is 0, IRQENTRY reflects the state of the highest priority pending enabled IRQ interrupt. If
the active IRQ interrupt is cleared in IRQn, then IRQENTRY is immediately updated with the vector
of the next highest priority pending enabled IRQ interrupt.
• If IERAW is 1, IRQENTRY reflects the state of the highest priority pending IRQ interrupt (enabled
or not). If the active IRQ interrupt is cleared in IRQn, then IRQENTRY is immediately updated with
the vector of the next highest priority pending IRQ interrupt (pending or not).
Events cause their matching bit in the FIQ or IRQ register (depending on the event priority) to be cleared
to 0. An event is cleared by writing a 1 to the corresponding bit in the FIQ or IRQ register. Writing a 1 to
the corresponding bit sets the bit back to a 1. Writing a 0 to an event bit does not affect its value.
The AINTC has two methods for enabling and disabling interrupts: immediate or delayed, based on the
setting of the IDMODE bit in the INTCTL register. When 0 (default), clearing an interrupt's EINT bit has an
immediate effect. The prioritizer removes the disabled interrupt from consideration and adjusts the
IRQ/FIQENTRY value correspondingly. If no other interrupts are pending, then the IRQz/FIQz output to
the ARM may also go inactive. Enabling the interrupt if it is already pending takes immediate affect. This is
shown in Figure 8-3 .
Figure 8-3. Immediate Interrupt Disable/Enable
If IDMODE is 1, then the EINT effect is delayed. Essentially, the active interrupt status is latched until
cleared by the ARM. If EINT is cleared, the prioritizer continues to use the interrupt and the IRQz/FIQz
remains active. Once the ARM clears the pending interrupt, further interrupts are disabled. In the same
way, setting EINT does not cause the previously pending interrupt event to become enabled until it has
been cleared first. The disable operation is shown in Figure 8-4 .
ARM Interrupt Controller (AINTC)90 SPRUEP9A – May 2008
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