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List of Tables
3-1 Exception Vector Table for ARM ......................................................................................... 22
3-2 Different Address Types in ARM System ............................................................................... 24
3-3 ITCM/DTCM Memory Map ................................................................................................ 26
3-4 TCM Status Register Field Descriptions ................................................................................ 26
3-5 TCM Region Setup Register Field Descriptions ........................................................................ 27
3-6 ITCM/DTCM Size Encoding............................................................................................... 27
5-1 PLLC1 Output Clocks ...................................................................................................... 39
5-2 PLLC2 Output Clock ....................................................................................................... 42
5-3 PLL and Reset Controller Module Instance Table ..................................................................... 45
5-4 PLL and Reset Controller Registers ..................................................................................... 45
5-5 Peripheral ID Register (PID) Field Descriptions ........................................................................ 46
5-6 Reset Type Status Register (RSTYPE) Field Descriptions ........................................................... 46
5-7 PLL Control Register (PLLCTL) Field Descriptions .................................................................... 47
5-8 PLL Multiplier Control Register (PLLM) Field Descriptions ........................................................... 48
5-9 PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions .................................................... 49
5-10 PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions .................................................... 50
5-11 PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions .................................................... 51
5-12 Bypass Divider Register (BPDIV) Field Descriptions .................................................................. 52
5-13 PLL Controller Command Register (PLLCMD) Field Descriptions................................................... 52
5-14 PLL Controller Status Register (PLLSTAT) Field Descriptions ....................................................... 53
5-15 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions ........................................ 54
5-16 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ........................................... 55
5-17 Clock Enable Control Register (CKEN) Field Descriptions ........................................................... 57
5-18 Clock Status Register (CKSTAT) Field Descriptions .................................................................. 58
5-19 SYSCLK Status Register (SYSTAT) Field Descriptions .............................................................. 59
5-20 PLL Controller Divider n Register (PLLDIV n) Field Descriptions .................................................... 60
6-1 Module Configuration ...................................................................................................... 64
6-2 Module States .............................................................................................................. 65
6-3 IcePick Emulation Commands ............................................................................................ 66
6-4 PSC Interrupt ............................................................................................................... 67
6-5 PSC Interrupt Events ...................................................................................................... 67
6-6 Power and Sleep Controller (PSC) Registers .......................................................................... 69
6-7 Peripheral Revision and Class Information Register (PID) Field Descriptions ..................................... 70
6-8 Interrupt Evaluation Register (INTEVAL) Field Descriptions ......................................................... 70
6-9 Module Error Pending Register 0 (MERRPR0) Field Descriptions .................................................. 71
6-10 Module Error Pending Register 1 (MERRPR1) Field Descriptions .................................................. 71
6-11 Module Error Clear Register 0 (MERRCR0) Field Descriptions ..................................................... 72
6-12 Module Error Clear Register 1 (MERRCR1) Field Descriptions ..................................................... 72
6-13 Power Domain Transition Command Register (PTCMD) Field Descriptions ....................................... 73
6-14 Power Domain Transition Status Register (PTSTAT) Field Descriptions ........................................... 73
6-15 Power Domain Status Register (PDSTAT0) Field Descriptions ...................................................... 74
6-16 Power Domain Control Register (PDCTL0) Field Descriptions ...................................................... 75
6-17 Module Status n Register (MDSTAT n) Field Descriptions ............................................................ 76
6-18 Module Control n Register (MDCTL n) Field Descriptions ............................................................. 77
7-1 Power Management Features ............................................................................................ 80
8-1 ARM Interrupt Map ......................................................................................................... 87
8-2 ARM Interrupt Controller (AINTC) Registers............................................................................ 91
8-3 Fast Interrupt Request Status Register 0 (FIQ0) Field Descriptions ................................................ 92
8-4 Fast Interrupt Request Status Register 1 (FIQ1) Field Descriptions ................................................ 92
SPRUEP9A – May 2008 List of Tables 9
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