User manual

7.1 Overview
7.2 PSC and PLLC Overview
Overview www.ti.com
In many applications, there may be specific requirements to minimize power consumption for both power
supply (or battery) and thermal considerations. There are two components to power consumption: active
power and leakage power. Active power is the power consumed to perform work and scales roughly with
clock frequency and the amount of computations being performed. Active power can be reduced by
controlling the clocks in such a way either to operate at a clock setting just high enough to complete the
required operation in the required timeline or to run at a clock setting until the work is complete and then
drastically cut the clocks (that is, to PLL Bypass mode) until additional work must be performed. Leakage
power is due to static current leakage and occurs regardless of the clock rate. Leakage, or standby power,
is unavoidable while power is applied and scales roughly with the operating junction temperatures.
Leakage power can only be avoided by removing power completely from a device.
The TMS320DM646x DMSoC has several means of managing the power consumption, as detailed in the
following sections. There is extensive use of automatic clock gating in the design as well as
software-controlled module clock gating to not only reduce the clock tree power, but to also reduce
module power by basically freezing its state while not operating. Clock management allows you to slow
down the clocks on the chip in order to reduce switching power. In particular, the DM646x DMSoC
includes all of the power management features described in Table 7-1 .
Table 7-1. Power Management Features
Power Management Features Description
Clock Management
PLL power-down The PLLs can be powered-down when not in use to reduce switching power
Module clock ON/OFF Module clocks can be turned on/off to reduce switching power
Module clock frequency scaling Module clock frequency can be scaled to reduce switching power
ARM and DSP Sleep Management
ARM Wait-for-Interrupt sleep mode Disable ARM clock to reduce active power
DSP sleep modes The DSP can be put into sleep mode to reduce switching power
I/O Management
3.3 Volt I/O power-down The 3.3 V I/Os can be powered-down to reduce I/O cell power
USB Phy power-down The USB Phy can be powered-down to reduce USB I/O power
The power and sleep controller (PSC) plays an important role in managing system clock on/off, and reset.
Similarly, the PLL controller (PLLC) plays an important role in device clock generation. The PSC and the
PLLC are mentioned throughout this chapter. For detailed information on the PSC, see Chapter 6 . For
detailed information on the PLLC, see Chapter 5 and the device-specific data manual.
80 Power Management SPRUEP9A – May 2008
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