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6.6.9 Power Domain Status Register (PDSTAT0)
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The power domain status register (PDSTAT0) is shown in Figure 6-11 and described in Table 6-15 .
Figure 6-11. Power Domain Status Register (PDSTAT0)
31 16
Reserved
R-0
15 12 11 10 9 8 7 5 4 0
Reserved EMUIHB Reserved PORDONE POR Reserved STATE
R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
Table 6-15. Power Domain Status Register (PDSTAT0) Field Descriptions
Bit Field Value Description
31-12 Reserved 0 Reserved
11 EMUIHB Emulation alters domain state.
0 Interrupt is not active.
1 Interrupt is active.
10 Reserved 0 Reserved
9 PORDONE Power_On_Reset (POR) Done status
0 Power domain POR is not done.
1 Power domain POR is done.
8 POR Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power domain
including all modules in the domain.
0 Power domain POR is asserted.
1 Power domain POR is de-asserted.
7-5 Reserved 0 Reserved
4-0 STATE Power Domain Status
0 Power domain is in the off state.
1 Power domain is in the on state.
Power and Sleep Controller (PSC)74 SPRUEP9A – May 2008
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