User manual

6.6.5 Module Error Clear Register 0 (MERRCR0)
6.6.6 Module Error Clear Register 1 (MERRCR1)
PSC Registers www.ti.com
The module error clear register 0 (MERRCR0) clears the corresponding interrupt bit set (M[ n]) in the
module error pending register 0 (MERRPR0) and the module status n register (MDSTAT n) interrupt bit
field for modules 0-31. MERRCR0 is shown in Figure 6-7 and described in Table 6-11 .
Figure 6-7. Module Error Clear Register 0 (MERRCR0)
31 0
M
W-0
LEGEND: W = Write only; - n = value after reset
Table 6-11. Module Error Clear Register 0 (MERRCR0) Field Descriptions
Bit Field Value Description
31-0 M[ n] Module interrupt clear bit for modules 0-31.
0 A write of 0 has no effect.
1 Clears module interrupt n.
The module error clear register 1 (MERRCR1) clears the corresponding interrupt bit set (M[ n]) in the
module error pending register 1 (MERRPR1) and the module status n register (MDSTAT n) interrupt bit
field for modules 32-45. MERRCR1 is shown in Figure 6-8 and described in Table 6-12 .
Figure 6-8. Module Error Pending Register 1 (MERRCR1)
31 16
Reserved
R-0
15 14 13 12 4 3 0
Reserved M Reserved M
R-0 R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
Table 6-12. Module Error Clear Register 1 (MERRCR1) Field Descriptions
Bit Field Value Description
31-14 Reserved 0 Reserved
13 M[ n] Module interrupt clear bit for module 45.
0 A write of 0 has no effect.
1 Clears module interrupt n.
12-4 Reserved 0 Reserved. (Modules 36-44 are reserved. See Table 6-1 .)
3-0 M[ n] Module interrupt clear bit for modules 32-35.
0 A write of 0 has no effect.
1 Clears module interrupt n.
72 Power and Sleep Controller (PSC) SPRUEP9A – May 2008
Submit Documentation Feedback