User manual

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9.6.4 Transport Stream Interface (TSIF) Control ................................................................... 106
9.6.5 Video Source Clock Control and Disable ..................................................................... 106
9.6.6 PWM Control ..................................................................................................... 106
9.6.7 EDMA3 Transfer Controller (EDMA3TC) Burst Size Configuration ....................................... 106
9.6.8 ARM Memory Wait State Control .............................................................................. 107
9.7 Bandwidth Management ................................................................................................. 107
9.7.1 Bus Master DMA Priority Control .............................................................................. 107
9.8 Emulation Control ......................................................................................................... 108
9.8.1 Set Emulator Suspend Source ................................................................................. 108
9.9 Clock and Oscillator Control ............................................................................................. 109
9.10 System Control Register Descriptions ................................................................................. 109
10 Reset ..................................................................................................................... 111
10.1 Reset Overview ........................................................................................................... 112
10.2 Reset Pins ................................................................................................................. 112
10.3 Types of Reset ............................................................................................................ 113
10.3.1 Power-On Reset (POR) ........................................................................................ 113
10.3.2 Warm Reset ..................................................................................................... 113
10.3.3 Maximum (Max) Reset ......................................................................................... 114
10.3.4 System Reset ................................................................................................... 114
10.3.5 Module Reset ................................................................................................... 114
10.3.6 DSP Local Reset ................................................................................................ 114
10.3.7 Test and Emulation Reset ( TRST pin) ....................................................................... 115
10.4 Default Device Configurations .......................................................................................... 115
10.4.1 Device Configuration Pins ..................................................................................... 115
10.4.2 PLL and Clock Configuration .................................................................................. 116
10.4.3 ARM Boot Mode Configuration ............................................................................... 117
10.4.4 EMIFA Configuration ........................................................................................... 118
10.4.5 PCI Enable (PCIEN) Operation ............................................................................... 118
10.4.6 DSP Boot Mode (DSP_BT) Configuration ................................................................... 119
11 Boot Modes ............................................................................................................ 121
12 ARM-DSP Integration .............................................................................................. 123
12.1 Introduction ................................................................................................................ 124
12.2 Shared Peripherals ....................................................................................................... 124
12.3 Shared Memory ........................................................................................................... 126
12.3.1 ARM Internal Memories ........................................................................................ 126
12.3.2 DSP Memories .................................................................................................. 126
12.3.3 External Memories .............................................................................................. 126
12.4 ARM-DSP Interrupts ...................................................................................................... 127
12.5 ARM Control of DSP Boot, Clock, and Reset ......................................................................... 128
12.5.1 DSP Boot ........................................................................................................ 128
12.5.2 DSP Module Clock ON/OFF .................................................................................. 129
12.5.3 DSP Reset ....................................................................................................... 130
A Revision History ..................................................................................................... 133
6 Contents SPRUEP9A – May 2008
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