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5.4.15 SYSCLK Status Register (SYSTAT)
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The SYSCLK status register (SYSTAT) is shown in Figure 5-18 and described in Table 5-19 . Indicates
SYSCLK n status. Actual default is determined by the actual clock status, which depends on the D nEN bit
in the PLL controller divider n register (PLLDIV n).
Figure 5-18. SYSCLK Status Register (SYSTAT)
31 16
Reserved
R-0
15 9 8 7 6 5 4 3 2 1 0
Reserved SYS9ON
(1)
SYS8ON
(1)
Rsvd SYS6ON
(1)
SYS5ON
(1)
SYS4ON
(1)
SYS3ON
(1)
SYS2ON
(1)
SYS1ON
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
(1)
For PLL1 only, not supported for PLL2.
Table 5-19. SYSCLK Status Register (SYSTAT) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Reserved
8 SYS9ON SYSCLK9 on status. For PLL1 only, not supported for PLL2.
0 Off
1 On
7 SYS8ON SYSCLK8 on status. For PLL1 only, not supported for PLL2.
0 Off
1 On
6 Reserved 0 Reserved
5 SYS6ON SYSCLK6 on status. For PLL1 only, not supported for PLL2.
0 Off
1 On
4 SYS5ON SYSCLK5 on status. For PLL1 only, not supported for PLL2.
0 Off
1 On
3 SYS4ON SYSCLK4 on status. For PLL1 only, not supported for PLL2.
0 Off
1 On
2 SYS3ON SYSCLK3 on status. For PLL1 only, not supported for PLL2.
0 Off
1 On
1 SYS2ON SYSCLK2 on status. For PLL1 only, not supported for PLL2.
0 Off
1 On
0 SYS1ON SYSCLK1 on status.
0 Off
1 On
SPRUEP9A – May 2008 PLL Controller 59
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