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5.4.14 Clock Status Register (CKSTAT)
PLL Controller Register Map www.ti.com
The clock status register (CKSTAT) is shown in Figure 5-17 and described in Table 5-18 . Clock status for
all clocks, except SYSCLK n. CKSTAT is not used on PLL2.
Figure 5-17. Clock Status Register (CKSTAT)
31 16
Reserved
R-0
15 4 3 2 1 0
Reserved BPON Reserved AUXEN
R-0 R-1 R-0 R-0
LEGEND: R = Read only; - n = value after reset
Table 5-18. Clock Status Register (CKSTAT) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reserved
3 BPON SYSCLKBP on status.
0 Off
1 On
2-1 Reserved 0 Reserved
0 AUXEN AUXCLK on status.
0 Off
1 On
PLL Controller58 SPRUEP9A – May 2008
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