User manual

5.4.13 Clock Enable Control Register (CKEN)
www.ti.com PLL Controller Register Map
The clock enable control register (CKEN) is shown in Figure 5-16 and described in Table 5-17 . Clock
enable control for miscellaneous output clocks. CKEN is not used on PLL2.
Figure 5-16. Clock Enable Control Register (CKEN)
31 16
Reserved
R-0
15 1 0
Reserved AUXEN
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 5-17. Clock Enable Control Register (CKEN) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 AUXEN AUXCLK enable. The actual clock status is shown in the clock status register (CKSTAT).
0 Clock is disabled.
1 Clock is enabled.
SPRUEP9A – May 2008 PLL Controller 57
Submit Documentation Feedback