User manual

5.4.12 PLLDIV Ratio Change Status Register (DCHANGE)
www.ti.com PLL Controller Register Map
The PLLDIV ratio change status register (DCHANGE) is shown in Figure 5-15 and described in
Table 5-16 . Indicates if SYSCLK n divide ratio has been modified.
Note: On the DM646x DMSoC, all PLL1 SYSCLK n dividers are programmable but you should not
change the divider value to maintain the clock ratios between various modules of the device.
You should only use the power-up default divider values for all PLL1 SYSCLK n dividers for
normal device operation.
PLL2 SYSCLK1 divider value is programmable and you may change the divider value for the
desired DDR2 memory controller clock frequency.
Figure 5-15. PLLDIV Ratio Change Status Register (DCHANGE)
31 16
Reserved
R-0
15 9 8 7 6 5 4 3 2 1 0
Reserved SYS9
(1)
SYS8
(1)
Rsvd SYS6
(1)
SYS5
(1)
SYS4
(1)
SYS3
(1)
SYS2
(1)
SYS1
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
(1)
For PLL1 only, not supported for PLL2.
Table 5-16. PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Reserved
8 SYS9 SYSCLK9 divide ratio is modified. SYSCLK9 divide ratio is changed during GO operation. For PLL1
only, not supported for PLL2.
0 Ratio has not been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK9 is not affected.
1 Ratio has been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK9 changes to the new divide ratio.
7 SYS8 SYSCLK8 divide ratio is modified. SYSCLK8 divide ratio is changed during GO operation. For PLL1
only, not supported for PLL2.
0 Ratio has not been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK8 is not affected.
1 Ratio has been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK8 changes to the new divide ratio.
6 Reserved 0 Reserved
5 SYS6 SYSCLK6 divide ratio is modified. SYSCLK6 divide ratio is changed during GO operation. For PLL1
only, not supported for PLL2.
0 Ratio has not been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK6 is not affected.
1 Ratio has been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK6 changes to the new divide ratio.
4 SYS5 SYSCLK5 divide ratio is modified. SYSCLK5 divide ratio is changed during GO operation. For PLL1
only, not supported for PLL2.
0 Ratio has not been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK5 is not affected.
1 Ratio has been modified. When the GOSET bit in the PLL controller command register (PLLCMD) is
set, SYSCLK5 changes to the new divide ratio.
SPRUEP9A – May 2008 PLL Controller 55
Submit Documentation Feedback