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5.4.8 Bypass Divider Register (BPDIV)
5.4.9 PLL Controller Command Register (PLLCMD)
PLL Controller Register Map www.ti.com
The bypass divider register (BPDIV) is shown in Figure 5-11 and described in Table 5-12 . Bypass divider
controls the divider for SYSCLKBP. BPDIV is not used on PLL2.
Figure 5-11. Bypass Divider Register (BPDIV)
31 16
Reserved
R-0
15 14 5 4 0
BPDEN Reserved RATIO
R/W-1 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 5-12. Bypass Divider Register (BPDIV) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 BPDEN Bypass divider enable.
0 Disable
1 Enable
14-5 Reserved 0 Reserved
4-0 RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
The PLL controller command register (PLLCMD) is shown in Figure 5-12 and described in Table 5-13 .
Contains command bits for various operations. Writes of 1 initiate command; writes of 0 clear the bit, but
have no effect.
Figure 5-12. PLL Controller Command Register (PLLCMD)
31 16
Reserved
R-0
15 1 0
Reserved GOSET
R-0 R/W0C-0
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; - n = value after reset
Table 5-13. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 GOSET GO bit for SYSCLK n phase alignment.
0 Clear bit (no effect)
1 Phase alignment
PLL Controller52 SPRUEP9A – May 2008
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